48
Canoga Perkins
Figure 4-2.
Typical High
Speed 2270
Modem
Application
4.3 Transmit Section
The data and clock signals input to the interface are converted to 5V logic signals for use by the
modem circuit. These signals then pass through the loopback and test pattern selectors to be
processed by the clock-correction circuit. Above 9 Mbps, the duty cycle of any transmit clock is
corrected to approximately 50%.
The logic signals are then converted to the ECL signals used for modulation. This modulation
uses a proprietary pulse width (PWM) encoding scheme. This signal drives the laser modulator
to generate the optical signal for transmission over the fiber optic cable.
This optical signal, and the standard A-Lead interface voltage signals, can be seen in Figure
4-3. Note how the pulsed light transitions relate directly to the actual data being transmitted,
and to the clock input from the modem.
The fast modulation used in the 2270 provides short 6-18 nanosecond pulses. These pulses are
realized on every clock edge, and the pulse width is dependent on the actual data being trans-
mitted. The time between these pulses is appropriate to the speed at which the data is being
transmitted. Below 9 Mbps the pulse positions are also sensitive to the duty cycle of the trans-
mit clock.
4.4 Receive Section
The duty cycle of the optical signal is close to 50% only at 20 Mbps. It reduces proportionally
with the data rate such that it is only 0.0025% at 1 kbps.
A special optical receiver circuit converts the incoming signal to ECL level for demodulation. The
clock is extracted by a very simple method which ensures a good Bit Count Integrity (BCI). The
data is dependent on sampling the width of each pulse. These are converted to 5V logic levels
which are passed through the loopback and test pattern detect circuits before connecting to the
interface.
4.5 Full Rate Agility
The 2270 operates to full specifications over a range of rates from 1 kbps to 20 Mbps. Changing
data rates does not require resetting switches or jumpers, except to set the clocking modes and
the speed of the internal or self-test rate clock.