34
Canoga Perkins
Figure 3-4.
Board Layout for
Programmable
Buffered Interface
Table 3-I. Delay Times for Programmable Buffered Interface
SW1 Position
Delay Time
(O)pen (C)losed
P53
1 2 3 4
C C C C
20 ns
O C C C
30 ns
C O C C
40 ns
O O C C
50 ns
C C O C
60 ns
O C O C
70 ns
C O O C
80 ns
O O O C
90 ns
C C C O
100 ns
O C C O
110 ns
C O C O
120 ns
O O C O
130 ns
C C O O
140 ns
O C O O
150 ns
C O O O
160 ns
O O O O
170 ns