Canberra 2015A, Руководство пользователя

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Input Amplifier K1
The differentiation network, POLE/ZERO cancellation circuitry and INPUT
POLARITY selection are located at the inverting input of K1. The SHAPING switch
S3 (sections S1 through S3 and P1 through P3) selects the passive differentiator capac-
itors C3, C4, and pole/zero control RV1 sets the degree of pole/zero compensation.
INPUT POLARITY is selected by switch S2. For (–) input polarity, gain is determined
by R23 and R15. With (+) input polarity, the gain is determined by the combination of
R23, R15, R12, and R13. Diode D1 is a fast switching protection diode for overload
signals, enhancing good overload recovery.
Gain Amplifier K2
Amplifier K2 is an inverting gain amplifier. Its gain is controlled by the ratio of the se-
ries combination of input resistors R46 through R51, selected by the COARSE GAIN
switch S1a (section R1), and the feedback resistor R65. The base-emitter of Q31 is re-
verse biased as a zener diode. It, and diodes D3, D4 and base-collector of Q31 provide
overload protection, enhancing good overload recovery. Capacitor C35 ac couples the
signal to the amplifier summing junction. Front panel control RV2, resistors R92 and
R65 form the feedback network which controls the FINE GAIN function.
Integrator Amplifier A5
ACTIVE INTEGRATOR A5 provides complex pole pairs where the locus of poles are
equidistant from the abscissa on the S-plane. The real part of the complex poles equal
that of the input differentiator. The real pole of the last integrator is 1.6 times this
value. Active filter networks for A5 are selected by the SHAPING switch S3 (sections
Cl, C2, C3, and El, E2, and E3) for the desired time constant.
Amplifier A5 is a wide band, high slew rate, integrated circuit operational amplifier. It
is connected in a non-inverting configuration with a dc gain of 2, determined by R5
and R6.
The OUTPUT of integrator A5 is connected through an RC filter network, R17, R24,
and C15 back to the summing junction of gain amplifier K2. The integrator also serves
as a buffer providing the necessary dc stabilization for gain amp K2.
Amp OUTPUT Integrator and Driver
The unipolar OUTPUT amplifier is comprised of A3 and a power OUTPUT driver Ql,
Q2, and 03. Integrated circuit A3 is a wide band, high slew rate operational amplifier.
The overall amplifier (op-amp and driver) provides an inverting gain of 2 with single
pole integration (C25, C26,and R35) to minimize noise introduced after the ACTIVE
INTEGRATOR A5.
The OUTPUT driver transistors are connected Class “AB”. Diodes D11, D14, and cur-
rent source Q2 form the biasing network for the OUTPUT transistors.
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Circuit Description