Document type:
Title:
Revision date:
Revision:
User's Manual (MUT)
Mod. N957 8k Multi-Channel Analyzer
28/05/2012
6
NPO:
Filename:
Number of pages:
Page:
00105/04:N957x.MUTx/06 N957_REV6
35
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3.4 Firmware revision register (0x02, r)
Bit
Name
Function
15..8 x
FPGA firmware revision (x.y)
7..0
y
FPGA firmware revision (x.y)
3.5 Firmware download register (0x03, r/w)
Bit
Name
Function
15..0 FLDATA
Allows to read/write words from/to the on-board flash memory. Must be
accessed only through software library API calls.
Register default value = 0x0000.
3.6 Flash Enable register (0x04, r/w)
Bit
Name
Function
0 FLENA Allows to enable the flash access for read/write operation.
Should be accessed only through software library API calls
Register default value = 0.
3.7 Pulser register (0x05, r/w)
Bit
Name
Function
15..0 Pulse
width A write access to this register enables a PULSER signal on the board
whose duration is equal to the value written. (1.6 µs * register value)
Register default value = 0x0000.
3.8 DAC register (0x06, r/w)
Bit
Name
Function
15..0 DAC
value Sets DAC value when module is in DAC TEST MODE (see § 3.3)
Register default value = 0x0000.
3.9 Block Dimension register (0x07, r/w)
Bit
Name
Function
15..0 BLDIM
Dimension of the next data block to read; write to BLDIM the number of
samples that the User want to convert/read (through the USB port)
Register default value = 0x0020. (64 byte packet)
