Document type:
Title:
Revision date:
Revision:
User's Manual (MUT)
Mod. N957 8k Multi-Channel Analyzer
28/05/2012
6
NPO:
Filename:
Number of pages:
Page:
00105/04:N957x.MUTx/06 N957_REV6
35
11
2.7 Technical specification table
Table 2.2: Mod. N957 Technical Features
No. of ADC channels
1
Input signals
Unipolar (positive) or bipolar, 300 mV ÷ 10 V range,
rise time> 0.1 µs
Resolution
13 bit (8192 channels - 8064 valid if sliding scale enabled see 2.8)
ADC Conversion time
0.8 µs
Dead Time
4.8 µs
LSB
1.22 mV
Gate
Signal must occur prior to and must extend for at least 0.2-
μ
s after
the peak (in External Gate mode);
Maximum transfer rate
30 Mbyte/s (USB2.0); 75 Kbytes/s (USB1.1)
Differential Non-Linearity
< 1% from 5% to 95% of input FSR (500 mV ÷ 9.5 V)
Integral Non-Linearity
< 0.065% from 5% to 95% of input FSR (500 mV ÷ 9.5 V)
Gain Instability:
<+150 ppm/°C
USB port
Compatible with USB 1.1 and USB 2.0
30Mbyte/s (USB 2.0 Bulk Transaction Protocol)
3m maximum cable length (longer distance can be achieved with
commercial off-the-shelf products)
I/O signals
NIM/TTL; selected via internal switch SW1 on PCB (see Fig. 2.2)
Discriminator Threshold
Software programmable, 0 mV ÷ 500 mV range, 100 steps
2.8 Analog to digital conversion
The input stage of the module is basically a linear stretcher which detects the input peak
value, while the gate is active, and keeps such value until the end of conversion.
Conversion can be triggered automatically (Auto Gate mode) or externally (External Gate
mode), depending on Control register setting (see §
3.3
). In the
fi
rst case a discriminator,
with a threshold settable via N957_SetLLD function, enables the conversion, which is
active as long as the input signal is above such threshold. In the second case, an
external gate is fed to the module, via front panel Gate In connector.
The output of the peak section is converted by a 13 bit Fast ADC. The ADC section
supports the sliding scale technique to reduce the differential non-linearity consists in
adding a known value to the analog level to be converted, thus spanning different ADC
conversion regions with the same analog value. The known level is then digitally
subtracted after the conversion and the final value is sent to the threshold comparator.
If the sliding scale is enabled, it reduces slightly the dynamic range of the ADC: the 13-bit
digital output is valid from 0 to 8063, while the values from 8064 to 8191 are not correct.
