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User's Manual (MUT)
Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer
04/05/2016
12
NPO:
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00100/09:5740x.MUTx/12
DT5740_REV12.DOC
50
20
Both clocks can be generated from the internal oscillator (50 MHz) or from external clock input
(CLK IN). By default, board uses the internal clock as PLL reference (REF-CLK). External clock can
be selected by register access (bit[6] of 0x8100). The external clock signal must be differential
(LVDS, ECL, PECL, LVPECL, CML) with a jitter lower than 100ppm (see Table 2.3).
AD9520 configuration can be changed and stored into non-volatile memory. AD9520
configuration change is primarly intended to be used for external PLL reference clock frequency
change.
DT5740 locks to an external 50 MHz clock with default AD9520 configuration (see § 3.2.1).
Please contact CAEN technical support (see § 8) for more information and configuration tools.
Refer also to AD9520 data sheet for more details:
http://www.analog.com/static/imported-files/data_sheets/AD9520-3.pdf
(in case the active link above doesn’t work, copy and paste it on the internet browser)
3.2.1
PLL Mode
As introduced in § 3.2, the source of the REF-CLK signal can be external (see Fig. 3.2) on CLK-IN
front panel connector or internal from the 50 MHz local oscillator.
The user can configure the board to sense the external clock by setting bit[6] of the register
address 0x8100.
The following options are allowed:
1. 50 MHz internal clock source – It’s the standard operating mode, where the default AD9520
configuration doesn’t require to be changed. OSC-CLK = REF-CLK.
2. 50 MHz external clock source – In this case, it is not required to reprogram the AD9520
dividers, as the external clock reference is identical to the frequency of the internal oscillator.
CLK-IN = OSC-CLK = REF-CLK.
3. External clock source different from 50 MHz – In this case, it is necessary to re-program the
AD9520.
NOTE: please, contact CAEN (§ 8) for the feasibility of point 3 and to receive the PLL
programming file.
PLL programming files can then be loaded by the user by using the CAENUpgrader software tool.
See § 5.1 for the program description and documentation reference.
