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User's Manual (MUT)

Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer

04/05/2016

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00100/09:5740x.MUTx/12

DT5740_REV12.DOC

Functional Description

3.1

Analog Input

Input dynamic is 2V

= 50 Ω). A 10V

= 1 kΩ) dynamic is available on request. By means

of a 16-bit DAC it is possible to add up to a ±1V DC offset (±5V @10V

) in order to preserve the

full dynamic range also with unipolar positive or negative input signals.

The input bandwidth ranges from DC to 30 MHz by 2nd order linear phase anti-aliasing low pass
filter.

OpAmp

DAC

Vref

12 bit

ADC

Input

FPGA

-1

-2

Input Dynamic Range: 2 Vpp

Positive Unipolar

DAC = FSR

16 bit

Negative Unipolar

DAC = 0

Bipolar

DAC = FSR/2

Fig. 3.1: Input diagram

3.1.1

DC Offset Common Setting

Setting the DC offset requires a write access at register addresses 0x1n98. The DC offset value
will be then applied to all the 8 channels of group n.

3.1.2

DC Offset Individual Setting

It is possible to apply a 8-bit positive digital offset individually to each channel inside a group to
finely correct the baseline mismatch.

The two 32-bit registers that encode the eight unsigned values for group n (n = 0..7) are:

0x100 * n -> Correction values for channel oﬀset 0..3
0x100 * n -> Correction values for channel oﬀset 4..7

Please, see UM5483 - 740 Family Waveform Recording Firmware Registers document for details.

NOTE: DC Offset individual setting is supported from the mezzanine (AMC FPGA) firmware
revision 0.10 on.

Содержание DT5740

Страница 1: ...Technical Information Manual MOD DT5740 04 May 2016 Revision n 12 32 CHANNEL 12 BIT 65 MS S DIGITIZER MANUAL REV 12 NPO 00100 09 5740x MUTx 12 ...

Страница 2: ... for inaccuracies CAEN SpA reserves the right to modify its products specifications without giving any notice for up to date information please visit www caen it MADE IN ITALY We stress the fact that all the boards are made in Italy because in this globalized world where getting the lowest possible price for products sometimes translates into poor pay and working conditions for the people who make...

Страница 3: ... 4 OPTICAL LINK Connector 14 2 5 5 USB Port 14 2 5 6 12V DC Input 15 2 5 7 SPARE Link 15 2 6 OTHER FRONT PANEL COMPONENTS 15 2 6 1 Diagnostic LEDs 15 2 7 TECHNICAL SPECIFICATIONS TABLE 16 3 FUNCTIONAL DESCRIPTION 18 3 1 ANALOG INPUT 18 3 1 1 DC Offset Common Setting 18 3 1 2 DC Offset Individual Setting 18 3 2 CLOCK DISTRIBUTION 19 3 2 1 PLL Mode 20 3 2 2 Reducing the Sampling Frequency 21 3 2 3 D...

Страница 4: ...5 3 Timer Reset 36 3 6 DATA TRANSFER CAPABILITIES 37 3 6 1 Block Transfer 37 3 6 2 Single Data Transfer 37 3 7 OPTICAL LINK AND USB ACCESS 38 4 DRIVERS LIBRARIES 39 4 1 DRIVERS 39 4 2 LIBRARIES 39 5 SOFTWARE TOOLS 41 5 1 CAENUPGRADER 41 5 2 CAENCOMM DEMO 42 5 3 CAEN WAVEDUMP 43 5 4 DPP QDC DEMO SOFTWARE 44 6 HW INSTALLATION 45 6 1 POWER ON SEQUENCE 45 6 2 POWER ON STATUS 45 7 FIRMWARE AND UPGRADES...

Страница 5: ...ON DIAGRAM 19 FIG 3 3 TRIGGER OVERLAP 23 FIG 3 4 EVENT ORGANIZATION 27 FIG 3 5 BLOCK DIAGRAM OF TRIGGER MANAGEMENT 29 FIG 3 6 SELF TRIGGER GENERATION 30 FIG 3 7 TRIGGER REQUESTS RELATIONSHIP WITH MAJORITY LEVEL 0 31 FIG 3 8 TRIGGER REQUESTS RELATIONSHIP WITH MAJORITY LEVEL 1 AND TTVAW 0 32 FIG 3 9 TRIGGER REQUESTS RELATIONSHIP WITH MAJORITY LEVEL 1 AND TTVAW 0 33 FIG 3 10 TRIGGER CONFIGURATION ON ...

Страница 6: ...o Digital Converter most channel settings are performed over groups of 8 channels one group per ADC chip The DC offset is adjustable via a 16 bit DAC on each 8 channel group in the 1 V 2 Vpp or 5 V 10 Vpp range The ADC resolution and the sampling frequency make this digitizer well suited for mid slow detection systems e g inorganic scintillators coupled to PMTs gaseous detectors Each 8 channel gro...

Страница 7: ...sible to connect up to 8 ADC modules to a single A2818 Optical Link Controller or up to 32 using a A3818 4 link version Optical Link and USB accesses are internally arbitrated Table 1 1 Available items Code Description WDT5740XAAAA DT5740 32 Ch 12 bit 65 MS s Digitizer 192kS ch EP3C16 SE WDT5740CXAAA DT5740C 10Vpp input 32 Ch 12 bit 65MS s Digitizer 192kS ch EP3C16 SE WDT5740DXAAA DT5740D 32 Ch 12...

Страница 8: ...1 2 Block Diagram DAC AMC FPGA ADC MEMORY CONTROLLER ADC BUFFERS x32 channels ROC FPGA Readout control Optical link control USB interface control Trigger control External interface control MUX OSC CLOCK MANAGER AD9520 LOCAL BUS CLK IN TRG IN GPI USB INPUTS FRONT PANEL GPO OPTICAL LINK Fig 1 1 Mod DT5740 Block Diagram The function of each block will be explained in detail in the subsequent sections...

Страница 9: ... IF THE OPERATING INSTRUCTIONS ARE NOT FOLLOWED CAEN provides the specific document Precautions for Handling Storage and Installation available in the documentation tab of the product web page that the user is mandatory to read before to operate with CAEN equipment 2 2 Power Requirements The DT5740 module is powered by the external AC DC stabilized power supply provided with the digitizer and incl...

Страница 10: ...tomatic control is managed by the ROC FPGA firmware from revision 4 4 on The user can manually set the fan speed through the bit 3 of the Fan Speed Control register Hardware revision 4 and ROC FPGA firmware revision 4 4 Bit 3 0 default sets the automatic fan speed control Bit 3 1 sets HIGH the fan speed Hardware revision 4 and ROC FPGA firmware revision 4 4 Bit 3 0 default sets LOW the fan speed B...

Страница 11: ... User s Manual MUT Mod DT5740 32 Channel 12bit 65MS s Digitizer 04 05 2016 12 NPO Filename Number of pages Page 00100 09 5740x MUTx 12 DT5740_REV12 DOC 50 11 2 4 Front and Back Panel Fig 2 2 Mod DT5740 front panel Fig 2 3 Mod DT5740 back panel ...

Страница 12: ...tion Analog input single ended input dynamics 2Vpp Zin 50Ω DT5740C 10Vpp Zin 1kΩ Mechanical specifications Two ERNI SMC 114805 Dual Row 68pin connectors Even channels 0 2 30 are also available on MCX coaxial connectors To use the 16 MCX channels the provided flat cable must be plugged between the lower and upper ERNI connectors see Fig 2 5 Fig 2 5 Flat cable pug for ERNI to MCX input channels All ...

Страница 13: ... operations incorrect alignment may lead to connector damage 2 5 2 CONTROL Connectors Function GPO digital output connector NIM TTL on Rt 50Ω to propagate the internal trigger sources the channel probes i e signals from the mezzanines GPI signal according to register addresses 0x8110 and 0x811C or the motherboard probes i e signals from the motherboard like the Run signal ClkOut signal ClockPhase ...

Страница 14: ...r Function Optical LINK connector for data readout and flow control up to 80 MB s transfer rate Daisy chainable Compliant to Multimode 62 5 125μm cable featuring LC connectors on both sides CAEN provides optical fiber cable selection for A3818 and A2818 Controllers see Table 1 1 with duplex connector on the controller side and two simplex connectors on the digitizer side the simplex connector with...

Страница 15: ...ng LEDs Table 2 2 Front panel LEDs Name Colour Function CLK IN green Indicates that the external clock is enabled TTL green Indicates that the standard TTL is set for GPO TRG IN and GPI NIM green Indicates that the standard NIM is set for GPO TRG IN and GPI LINK green yellow Network present Data transfer activity USB green The right green LED indicates the network presence the left yellow LED sign...

Страница 16: ...O CONNECTORS CLK IN AMP Modu II AC coupled differential input clock LVDS ECL PECL LVPECL CML single ended NIM TTL available by A318 adapter Jitter 100ppm requested GPO LEMO General purpose digital output NIM TTL Rt 50 Ω GPI LEMO General purpose digital input NIM TTL Zin 50 Ω TRG IN LEMO External trigger digital input NIM TTL Zin 50 Ω MEMORY 192 kS ch Multi event Buffer divisible into 1 1024 buffer...

Страница 17: ... CONET proprietary protocol Up to 80 MB s transfer rate Daisy chainable it is possible to connect up to 8 or 32 ADC modules to a single Optical Link Controller respectively A2818 or A3818 USB USB 2 0 compliant Up to 30 MB s transfer rate DPP FW SUPPORTED DPP QDC firmware for the Charge to Digital Conversion supported only by DT5740D version FIRMWARE UPGRADE Firmware can be upgraded via USB Optical...

Страница 18: ... Dynamic Range 2 Vpp Positive Unipolar DAC FSR 16 bit Negative Unipolar DAC 0 Bipolar DAC FSR 2 Fig 3 1 Input diagram 3 1 1 DC Offset Common Setting Setting the DC offset requires a write access at register addresses 0x1n98 The DC offset value will be then applied to all the 8 channels of group n 3 1 2 DC Offset Individual Setting It is possible to apply a 8 bit positive digital offset individuall...

Страница 19: ...IT RAMCLK LOCAL BUS MUX Phase Detector CLK1 Sdiv Rdiv REFIN INTCLK CTRL Ldiv Odiv Ndiv Ldel Odel SYNCB VCXO Fig 3 2 Clock distribution diagram The module clock distribution takes place on two domains OSC CLK and REF CLK the former is a fixed 50MHz clock provided by an on board oscillator the latter provides the ADC sampling clock OSC CLK handles Local Bus communication between motherboard and mezz...

Страница 20: ...alog com static imported files data_sheets AD9520 3 pdf in case the active link above doesn t work copy and paste it on the internet browser 3 2 1 PLL Mode As introduced in 3 2 the source of the REF CLK signal can be external see Fig 3 2 on CLK IN front panel connector or internal from the 50 MHz local oscillator The user can configure the board to sense the external clock by setting bit 6 of the ...

Страница 21: ...mware processes the digitized input waveforms calculating an averaged value of the decimated 2n consecutive samples The self trigger is then issued as soon as an averaged value exceeds the programmed threshold see 3 4 3 Software trigger and external trigger are not affected by decimation option While the real sampling frequency doesn t change i e 62 5 MS s the decimation effect is to change the ra...

Страница 22: ...er signal allows to store a 31 bit counter value of the Trigger Time Tag TTT The counter representing a time reference like so the Trigger Logic Unit see 3 2 operates at a frequency of 125 MHz i e 8 ns that is to say ADC clock cycles Due to the way the acquired data are written into the board internal memory i e in 4 sample bunches the TTT counter is read every 2 trigger logic clock cycles which m...

Страница 23: ...vent is not reached yet this happens typically as the trigger occurs too early either with respect to the RUN_ACQUISITION command see 3 3 1 or with respect to a buffer emptying after a MEMORY_FULL status see 3 3 5 the trigger overlaps the previous one and the board is not enabled for accepting overlapped triggers As a trigger is refused the current buffer is not frozen and the acquisition continue...

Страница 24: ...ents It is possible to make events with a number of samples which depends on 0x8020 register setting smaller than the default value This register s value is given in number of memory locations According to the formula 3 NLOC 2 NS only values that are multiples of 3 are allowed for this register NOTE The value of NLOC must be set in order that the relevant number of samples does not exceed the buff...

Страница 25: ...24 of 2nd header word this bit identifies the event format with the default firmware it is reserved and must be 0 TRIGGER OPTIONS Bit 23 8 of 2nd header word starting from revision 4 6 of the ROC FPGA firmware these 16 bits can be programmed to provide different trigger information according to the setting of the bits 22 21 at registeraddress 0x811C Table 3 2 NOTE or ROC FPGA firmware revisions lo...

Страница 26: ...or all triggers TRIGGER TIME TAG Bit 31 0 of 4th header word It is the 31 bit Trigger Time Tag information 31 bit counter and 32nd bit as roll over flag which is the trigger time reference If the ETTT option is enabled then this field becomes the 32 less significant bits of the extended 48 bit trigger time tag information in addition to the 16 bits MSB of the TRG OPTIONS field 2nd event word Note ...

Страница 27: ...es Page 00100 09 5740x MUTx 12 DT5740_REV12 DOC 50 27 3 3 4 3 Event Format Examples Fig 3 4 shows the event format of the DT5740 digitizer as described in 3 3 4 NOTE data transfer starts from Channel 0 of Group 0 once all the data from one Group are transferred data transfer from the subsequent Group from 0 to 3 begins Fig 3 4 Event Organization ...

Страница 28: ...ting continues in the last available buffer As soon as one buffer is readout and becomes free the boards exits the FULL condition and can immediately accept a new trigger This way the FULL reflects the BUSY condition of the board i e inability to accept triggers NOTE when bit 5 1 the minimum number of circular buffers to be programmed is Nb 2 In some cases the BUSY propagation from the digitizer t...

Страница 29: ...anization and custom size settings and position with respect to the trigger given by the post trigger NOTE For the trigger management in the DPP QDC firmware operating please refer to the web available UM4874 DPP QDC User Manual The generation of a common acquisition trigger is based on different trigger sources configurable at register address 0x810C Software trigger External trigger Self trigger...

Страница 30: ..._TRG when the digitized input pulse goes over or under a configurable threshold according to bit 6 of register address 0x8000 see Fig 3 6 The threshold common to each group is set is set through the register address 0x1n80 n is the group number The self triggers of each group are ORed to generate a trigger request TRG_REQ The trigger requests are then propagated to the central trigger logic where ...

Страница 31: ...e takes place when Number of enabled trigger requests Majority level Supposing bits 3 0 FF i e all groups are enabled and bits 26 24 01 i e Majority level 1 a common trigger is issued whenever at least two of the enabled trigger requests are in coincidence within the programmed TTVAW The Majority level must be smaller than the number of trigger requests enabled via bits 3 0 mask By default bits 26...

Страница 32: ... are enabled with Majority level 1 and TTVAW is a value different from 0 GR1 THRESHOLD TRG_REQ 0 TRG_REQ 1 GR0_CHx enabled IN GR0 THRESHOLD TRIGGER Maj lev 1 GR1_CHx enabled IN OR signal TTVAW Fig 3 8 Trigger requests relationship with Majority level 1 and TTVAW 0 NOTE with respect to the position where the common trigger is generated the portion of input signal stored depends on the programmed le...

Страница 33: ...ESHOLD TRG_REQ 0 TRG_REQ 1 GR0_CHx enabled IN GR0 THRESHOLD TRIGGER Maj lev 1 GR1_CHx enabled IN OR signal TTVAW Fig 3 9 Trigger requests relationship with Majority level 1 and TTVAW 0 In this case the common trigger is issued if at least two of the enabled trigger requests are instantaneously in coincidence no TTVAW is waited NOTE a practical example of making coincidences with the digitizer in t...

Страница 34: ...rigger and the External Trigger participate in the common acquisition trigger refer to the red path on top of Fig 3 10 A Trigger Out signal is also generated on the relevant front panel GPO connector NIM or TTL and allows to extend the trigger signal to other boards Thanks to its configurability see Fig 3 10 GPO can propagate out the OR of all the enabled trigger sources only the Software Trigger ...

Страница 35: ...al In this case the programming steps to perform are following described 1 Register 0x8110 on board n Enable the desired trigger request as Trigger Out signal on board n by bits 3 0 mask Disable Software Trigger and External Trigger as Trigger Out signal on board n bits 31 30 00 Set Trigger Out signal as the OR of the enabled trigger requests on board n bits 9 8 00 2 Register 0x811C on board n Con...

Страница 36: ...ar the data off the Output Buffer the event counter and performs a FPGAs global reset which restores the FPGAs to the default configuration It initializes all counters to their initial state and clears all detected error conditions 3 5 2 Memory Reset The Memory Reset clears the data off the Output Buffer The Memory Reset can be forwarded via either a write access at register address 0xEF28 whateve...

Страница 37: ...ogrammed number of events is available for readout the board sends an interrupt to the PC over the optical communication link not supported by USB Using Polling interrupts disabled by performing periodic read accesses to a specific register of the board it is possible to know the number of events present in the board and perform a BLT read of the specific size to read them out Using Continuous Rea...

Страница 38: ...cal Link Controller or up to 32 boards to a single A3818 PCIe Optical Link Controller Detailed information on CAEN PCI PCIe Controllers can be find at www caen it Home Products Modular Pulse Processing Electronics PCI PCIe Optical Controllers The parameters for read write accesses via optical link are Address Modifier Base Address data Width etc wrong parameter settings cause Bus Error Bit 3 at re...

Страница 39: ...raries including also demo and example programs represent a powerful base for users who want to develop customized applications for the digitizer control communication configuration readout etc CAENDigitizer is a library of functions designed specifically for the Digitizer family and it supports also the boards running the DPP firmware The CAENDigitizer library is based on the CAENComm library For...

Страница 40: ...5740x MUTx 12 DT5740_REV12 DOC 50 40 CAENComm and so the CAENDigitizer supports the following communication channels PC USB DT5740 PC PCI PCIe A2818 A3818 CONET DT5740 CONET2 Optical Link A2818 A3818 CAEN SW Tools USB 2 0 User s own SW DT5730 CAENComm CAENDigitizer Library A2818 driver A3818 driver USB driver PCI PCIe Fig 4 1 Block diagram of the software layers ...

Страница 41: ...mware license in case of pay firmware Upgrade the internal PLL Get the Board Info file useful in case of support CAENUpgrader can operate with Windows and Linux 32 and 64 bit OSs The program relies on the CAENComm and CAENVMELib libraries see 4 2 and requires third party Java SE 8 u40 or later to be installed NOTE Windows version of CAENUpgrader is stand alone i e only the communication driver nee...

Страница 42: ...ws for a full board configuration at low level by direct read write access to the registers and may be used as a debug instrument Fig 5 2 CAENComm Demo Java and LabVIEW graphical interface CAENComm Demo can operate with Windows OS 32 and 64 bit It requires CAENComm and CAEVMElib libraries as additional software to be installed see 4 2 The Demo is included in the CAENComm library Windows installati...

Страница 43: ...ontaining a list of parameters and instructions to start stop the acquisition read the data display the readout and trigger rate apply some post processing e g FFT and amplitude histogram save data to a file and also plot the waveforms using Gnuplot third party graphing utility www gnuplot info Fig 5 3 CAEN WaveDump CAEN WaveDump can operate with Windows and Linux OS 32 and 64 bit The program reli...

Страница 44: ...ng the DPP QDC firmware It is possible to set the communication parameters and DPP settings Waveforms and histograms can also be plotted in real time for one channel at a time and both waveforms and lists of time stamp and energy can be saved DPP QDC Demo Software is provided including C source files for developers DPP QDC Demo Software can operates with Windows OS 32 and 64 bit Installation packa...

Страница 45: ...rocedure 1 connect the 12V DC power supply to the DT5740 through the DC input rear connector 2 power up the DT5740 through the ON OFF rear switch See 2 5 to identify the relevant components 6 2 Power on Status At power on the module is in the following status the Output Buffer is cleared registers are set to their default configuration After the power on the front panel LEDs status is that only th...

Страница 46: ...mware is stored onto the on board FLASH memory Two copies of the firmware are stored in two different pages of the FLASH referred to as Standard STD and Backup BKP In case of default firmware the board is usually factory equipped with the same firmware version on both pages At power on a microcontroller reads the FLASH memory starting from the STD page and programs the module automatically loading...

Страница 47: ...ducts Modular Pulse Processing Electronics VME Digitizers Digitizer Model 7 1 1 Default Firmware File Description The extension of the programming default firmware file is CFA CAEN Firmware Archive which is a sort of archive format file aggregating all the default firmware files compatible with the same family of digitizers CFA and its name follows this general scheme x740_revX Y_W Z CFA where x74...

Страница 48: ...ort of archive format file aggregating all the firmware files compatible with the same DPP firmware and family of digitizers CFA and its name follows this general scheme x740D_DPP QDC_rev_X Y_135 Z CFA where the major revision number of the channel FPGA is fixed for the specific DPP algorithm and digitizer family 135 for DPP QDC and 740D The other fields have the same meaning as in the default fir...

Страница 49: ...t power on the microcontroller loads exactly the firmware copy from the STD page of the FLASH In this case when a failure occurs during the upgrade of the STD page of the FLASH which compromises the communication with the DT5740 the user can perform the following recovering procedure as first attempt Force the board to reboot loading the copy of the firmware stored on the BKP page of the FLASH For...

Страница 50: ...who need for product s return and repair have to fill and send the Product Return Form PRF in the Returns and Repairs area at Home Support Services describing the specific failure A printed copy of the PRF must also be included in the package to be shipped Contacts for shipping are reported on the website at Home Contacts 8 2 Technical Support Service CAEN makes available the technical support of ...

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