BVM BVME4000, Руководство пользователя

Страница: 72 / 87

BVME4000/6000 62
Copyright

1993,1995,1998,2001 BVM Ltd.
Appendix B CPU Cache Coherency and Bus Snooping
B.1 BVME4000 (MC68040)
The MC68040 is a third generation 68000 series processor with separate data and instruction caches
of 4Kbytes each. The cache unit supports full copyback caching, in addition to write-through caching
(as available on earlier processors), cache inhibited, and bus-serialised cache modes.
Copyback caching means that when data is written out by the program, it may only reach the cache,
and not the main memory. This poses cache coherency problems over those normally associated with
earlier 68000 series processors (e.g. 68030), as the main memory can contain stale data, affecting
DMA operations transferring data from dual-ported memory as well as to dual ported memory.
Bus serialisation is required as the 68040's internal architecture has a high degree of parallelism.
Reads and writes do not occur in the order in which they are defined by the programmer. Normally this
causes no problem as the 68040 will detect any clashes and synchronise them, but if accesses are
being made to I/O areas for example, the ordering of reads and writes are very important. Bus
serialised regions cause correct ordering of the reads and writes.
It follows on from the above that it is important to be able to define regions of the address space as
operating in different caching modes. This isn't strictly a caching issue, but is very relevant to the
operation of system and user software.
Use is made of the 68040's "Transparent Translation Registers" and MMU "Page Tables" to define the
caching mode for different regions of the address space. The 68LC040 also has an MMU, and
functions exactly the same way as a 68040 in this respect. On the 68EC040 however, although the
MMU is not available, the Transparent Translation Registers are still present, and can be used for this
function, although the strategy needs to be slightly different.
The 68040's Transparent Translation Registers contain an address and mask field to allow definition
of an address range to be used. They also contain fields to specify the relevant caching modes for the
defined region. There are four registers, two for data DTT0 and DTT1 and two for instructions ITT0
and ITT1.
The TT0 registers override the TT1 registers if there is any overlap, and undefined regions will be
accessed in the 68040's default mode (write-through caching enabled) if the MMU is disabled. If the
MMU is enabled (not on 68EC040) any regions undefined in the TT registers will be checked in the
Page Tables. The Page Tables relate to a 4 or 8KByte region, and the caching mode is specified in a
field of the page descriptor in a similar way to the TT registers.
On the BVME4000 with a 68040 or 68LC040 processor, a cache-inhibited, bus-serialised region can
be defined from $F0000000 to $FFFFFFFF for access to IP Memory, EPROM, SRAM, VMEbus A24,
VMEbus A16 & on-board registers for supervisor access. The rest of the address space is defined as
write-through caching for instructions and copy-back caching for data for supervisor mode. The page
descriptors would be used to define the regions for user-state accesses, allocated on a dynamic basis
(by operating system software). The values that need to be set into the 68040 TT registers to
implement this scheme are as follows:
DTT0 = $F00FA040, DTT1 = $00FFA020, ITT0 = NOT USED, ITT1 = $00FFA000
On the BVME4000 with a 68EC040 processor, a similar scheme as that for the 68040/68LC040 can
be set up. This gives an I/O region from $F0000000 to $FFFFFFFF for supervisor and user-state
access, with the rest of the address space defined as write-through caching for instructions and
copyback caching for data for supervisor and user-state access. The values that need to be set into
the 68EC040 TT registers to implement this scheme are as follows:
DTT0 = $F00FC040, DTT1 = $00FFC020,ITT0 = NOT USED, ITT1=$00FFC000