Bose Personalized Amplification System, Руководство по устранению неисправностей

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37
APPENDIX
1
2
3
4
5
6
7 8
9
10
11
12
13
14
A1
B1
Y1
A2
B2
Y2
GND
Y3
A3
B3
Y4
A4
B4
Vcc
A
B
Y
74HC00, Quad 2 Input Nand Gate
74LCX125 Quad Buffer
PIN CONFIGURATION
14
13
12
11
10
9
8 7
6
5
4
3
2
1
GND
V
CC
3B
3A
3Y
4Y
4B
4A
1A
1B
2Y
1Y
2A
2B
LOGIC SYMBOL
1A
1B
2A
2B
3A
1Y
3B
4A
4B
2Y
3Y
4Y
3
6
8
11
1
2
4
5
9
10
12
13
74LV08 Quad AND Gate
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DIR
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
GND B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
OE
V
CC
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1 DIR Direction
2, 3, 4, 5,
6, 7, 8, 9
A
0
to A
7
Data inputs/outputs
10 GND Ground (0 V)
18, 17, 16, 15,
14, 13, 12, 11
B
0
to B
7
Data inputs/outputs
19 OE Output enable input (active LOW)
20 V
CC
Positive supply voltage
74LV245 Octal Bus Transciever
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
1, 4, 9, 12 1A ± 4A Data inputs
2, 5, 10, 13 1B ± 4B Data inputs
3, 6, 8, 11 1Y ± 4Y Data Outputs
7 GND Ground (0 V)
14 V
CC
Positive supply voltage
1
2
3
4
5
6
7
1A
1B
1Y
2A
2B
2Y
GND
V
CC
4B
4A
4Y
3B
3A
3Y
14
13
12
11
10
9
8
74LV32 Quad AND Gate
Pin A ssign ment s for SOIC and DIP
Top View
CD4093BC Quad NAND Gate