Figure 5:
DDC Functional Block Diagram
The complex multiplication is then followed by either a finite impulse response (FIR) filter
or cascaded integrator-comb (CIC) filters with a FIR filter combined. The CIC filter has a
‘droop’ associated with it in the passband. In order to compensate for this droop, the CIC
filter is followed by a compensating FIR filter. Each filter type has its own decimator. This
whole process effectively reduces the sample rate and filters the signal to remove
adjacent channels, minimize aliasing, and maximize the received signal-to-noise ratio.
Note:
The use of the NCO converts the in-phase signal (I data) input of the receiver's
DD, SH and SHN processing paths to complex I and Q data output. See
Table 2
.
Triggers
Triggers provide a means of qualifying the storage of captured time domain IQ data
based on an external, periodic or frequency domain event. Triggering can be considered
a means of filtering signals of interest for the purposes of subsequent visualization
and/or analysis.
The following describes the different types of triggers and their common controls.
Selection of different types is mutually exclusive.
Frequency Domain Triggering
Frequency domain triggering relies on the embedded real-time FFT mechanism to
transform the sampled signal from the time domain to the frequency domain. The
RTSA7500 uses a 1024 point real-time FFT core embedded within the FPGA to transform
1024 time domain IQ samples to 1024 frequency domain FFT bins. Each bin is an
average of the spectral activity over a range of 125MHz divided by the DDC decimation
rate divided by the 1024 FFT points.
The frequency domain triggering supported by RTSA7500 is a level trigger type, used to
capture any signal above the noise floor within a specified frequency range. The user
defines a single amplitude level within a frequency range. The frequency range
encompasses all FFT bins with center frequencies within the range defined by START
