20
SERIAL
↔
PARALLEL CONVERTER (38.4 kbps)
Appendix B. Block Diagram
PAPER END
SELECT
DCE/DTE
DETECTOR
CONTROL
STATUS
LED
DATA BIT 1
DATA BIT 2
DATA BIT 3
DATA BIT 4
DATA BIT 5
DATA BIT 6
DATA BIT 7
DATA BIT 8
STROBE
ACKNOWLEDGE
BUSY
DSR
RTS
DCD
DTR
CTS
RD
TD
GND
100K
PULL UP
NETWORK
PARALLEL
AND
SERIAL
PROCESSOR
REGULATOR
WITH
RESET
MONITOR
RESET
DIP SWITCH
SETTINGS FOR
RATE/LENGTH/PARITY
POWER
SUPPLY
DCD
RD
TD
DTR
DSR
RTS
CTS
+VIN
+V
-V
+5V
Содержание PI080A-R2
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