15
MULTIPORT CSU/DSU
Switch S1-7: Asynchronous Character Length
Set Switch S1-7 to configure the total number of asynchronous bits per
asynchronous character (when Switch S1-6 is set to “On”).
Table 3-6. Settings for Switch S1-7.
S1-7
Setting
Off
10 bits
On
11 bits
NOTE
The total number of bits in an asynchronous character is determined by
the sum of all start bits, data bits, stop bits, and parity bits. For
instance:
1 start bit + 8 data bits + 1 stop bit + 0 parity bits = 10 bits
Switch S1-8: Extended Signaling Rate
Use S1-8 to configure the frequency tolerance the CSU/DSU looks for in
asynchronous data rates (the actual variance from a given frequency level the
CSU/DSU will tolerate).
Table 3-7. Settings for Switch S1-8.
S1-8
Setting
Off
-2.5% to +1%
On
-2.5% to +2.3%
3.1.2 DIP S
WITCH
S
ET
S2
You can use the DIP switches on set S2 to configure the line rate, clock mode, force
RTS, and DSR status during local loop. Default settings are shown in
Table 3-8
. All
settings are shown in
Table C-2
. Detailed descriptions for each switch in the set
appear on
pages 15–17
.