Chapter2
BIOS Setup
2-14
SDRAM Cycle Time Tras/Trc
Determines SDRAM Trc Timing Value which is the minimum time from activate
to activation of the same bank.
Determines SDRAM Tras Timing Value which is the time from activate to
precharge of the same bank.
The Choices:
Auto
(default), 5/7, 6/8.
SDRAM RAS-to-CAS Delay
This field lets you insert a timing delay between the CAS and RAS strobe signals,
used when DRAM is written to, read from, or refreshed. Fast gives faster
performance; and Slow gives more stable performance. This field applies only
when synchronous DRAM is installed in the system.
The Choices: Auto
(default), 2, 3.
SDRAM RAS Precharge Time
If an insufficient number of cycle is allowed for RAS to accumulate its charge
before DRAM refresh, the refresh may be incomplete and the DRAM may fail to
retain data. Fast gives faster performance; and Slow gives more stable
performance. This field applies only when synchronous DRAM is installed in the
system.
The Choices: Auto
(default), 2, 3.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh,
resulting in better system performance. However, if any program writes to this
memory area, a system error may result.
The Choices: Disabled
(default), Enabled
Video BIOS Cacheable
Select Enabled allows caching of the video BIOS, resulting in better system
performance. However, if any program writes to this memory area, a system error
may result.
The Choices: Disabled
(default), Enabled
