Benison V5, Руководство по обслуживанию

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BENISON V5
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applied to the modulator circuit after being passed through the mute switch (IC4, pins 9, 8).
2.
MODULATION CIRCUIT
The modulation circuit modulates the VCO oscillating signal (RF signal) using the microphone audio signal.
The audio signals change the reactance of a diode (D7) to modulate an oscillated signal at the VCO circuit
(Q20, Q23).The oscillated signal is amplified at the buffer-amplifiers (Q21,Q24), then applied to the T/R
switching circuit (D9, D10).
3.
DRIVE/POWER AMPLIFIER CIRCUITS
The signal from the VCO circuit passes through the T/R switching circuit (D9) and is amplified at the buffer
(Q19),drive (Q27) and power amplifier (Q26) to obtain 5 W of RF power (at 7.2 V DC). The amplified signal
passes through the antenna switching circuit (D11), and low-pass filter and is then applied to the antenna
connector. The bias current of the drive (Q27) and the power amplifier (Q26) is controlled by the APC
circuit.
4. APC CIRCUIT
The APC circuit (IC1A) protects the drive and the power amplifiers from excessive current drive, and
selects HIGH or LOW output power. The signal output from the power detector circuit (D28, D29) is applied
to the differential amplifier (IC1A, pin 2), and the
“
T1
”
signal from the expander (IC5, pin 11), controlled by
the CPU (IC8), is applied to the other input for reference. When the driving current is increased, input
voltage of the differential amplifier (pin 2) will be increased. In such cases the differential amplifier output
voltage (pin 1) is decreased to reduce the driving current.
3) PLL Synthesizer Circuit
1. PLL
The dividing ratio is obtained by sending data from the CPU (IC8) to pin 28 and sending clock pulses to pin
39 of the PLL IC (IC13). The oscillated signal from the VCO is amplified by the buffer (Q22) and input to pin
6 of IC13. Each programmable divider in IC13 divides the frequency of the input signal by N according to
the frequency data, to generate a comparison frequency of 12.5kHz.
2. PLL Loop Filter Circuit
If a phase difference is found in the phase comparison between the reference frequency and VCO output
frequency, the charge pump output (pin 8) of IC11 generates a pulse signal, which is converted to DC
voltage by the PLL loop filter and input to the varicap of the VCO unit for oscillation frequency control.
3. VCO Circuit
A PLL circuit provides stable oscillation of the transmit frequency and receive 1st LO frequency. The PLL
output compares the phase of the divided VCO frequency to the reference frequency. The PLL output
frequency is controlled by the divided ratio (N-data) of a programmable divider.The PLL circuit contains the
VCO circuit (Q20, Q23). The oscillated signal is amplified at the buffer-amplifiers (Q21, Q22) and then
applied to the PLL IC (IC11). The PLL IC contains a prescaler, programmable counter, programmable
divider and phase detector, etc. The entered signal is divided at the prescaler and programmable counter
section by the N-data ratio from the CPU. The divided signal is detected on phase at the phase detector
using the reference frequency. If the oscillated signal drifts, its phase changes from that of the reference
frequency, causing a lock voltage change to compensate for the drift in the oscillated frequency. A portion
of the VCO signal is amplified at the buffer-amplifier (Q24) and is then applied to the receive 1st mixer (Q28)
or transmit buffer-amplifier circuit (Q19) via the T/R switching diode (D9, D10).
4) CPU and Peripheral Circuits
1. LCD Display Circuit
The IC10 turns ON the LCD via segment and common terminals with 1/4 the duty and 1/3 the bias, at the
frame frequency is 100Hz.
2. Display Lamp Circuit
When the key is pressed, “H” is output form pin 34 of CPU (IC8) to the bases of Q15. Q15 then turn ON and
the LED (D14 – D22) light.