ADC16 Instruction Manual
– Rev A
Page 4
500 MHz and includes digital filters to remove
jitter from the reference clock input. The
Benchmark UltraLockDDS™ clock-system
outperforms two-stage PLL designs while
providing the frequency agility to handle the
special sample rates that are often required
for video transfers to and from film.
The Benchmark UltraLockDDS™ system
delivers consistent performance under all
operating conditions. Users should not
hesitate to lock the ADC16 to other clock
sources. The UltraLockDDS™ will remove
jitter from the external clock reference, and
supply a clean clock to the internal A/D
converters.
The predecessor of UltraLockDDS™ is
UltraLock™, Benchmark's pioneering jitter-
elimination technology. UltraLockDDS™
meets or exceeds the performance of
Benchmark's UltraLock™ system, but does
not use asynchronous sample rate conversion
(ASRC). The elimination of the ASRC
processing reduces system latency and
provides the most direct path from the A/D to
the digital interface.
The ADC16 is designed to perform gracefully
in the presence of errors and interruptions at
the clock reference input. The ADC16 will
even lock to an AES/EBU signal that has its
sample-rate bit status set incorrectly since
the sample rate is determined by measuring
the incoming signal. Lack of sample-rate
status bits or incorrectly set status bits will
not cause loss of audio.
The ADC16 is phase-accurate between
channels and between other ADC16 boxes
when locked to AES/EBU or word clock
reference signals. The word clock output from
one ADC16 may be connected to the clock
input on another ADC16 to expand the
number of phase-accurate conversion
channels.
