ADC16 Instruction Manual
Page 29
UltraLockDDS™ … What Is It?
Accurate audio conversion requires a very low-jitter conversion clock. Jitter can easily cause severe
inaccuracies if not adequately addressed, even when the device employs high-performance
converter chips.
UltraLockDDS™ is Benchmark's latest jitter-immune clock technology. The ADC16 is the first
device to employ Benchmark's new UltraLockDDS™ technology to eliminate all jitter-induced
performance problems.
Benchmark's new UltraLockDDS™ clock system utilizes the latest low-jitter clock technology
developed for high-frequency RF communications systems. The master oscillator is a low phase-
noise, temperature-compensated, fixed-frequency crystal oscillator with a +/- 2 PPM frequency
accuracy. This oscillator drives a 500 MHz Direct Digital Synthesis (DDS) system that generates a
3072 x WC system clock. This high-frequency clock is divided by 6 and distributed directly to the
A/D converters using a high-speed PECL clock distribution chip. Each of the 8 converters are driven
directly from a dedicated, matched-impedance transmission line.
Jitter attenuation is achieved with digital filters in a custom FPGA that controls the DDS system. All
jitter-induced distortion artifacts are well below audibility under all operating conditions. Jitter-
induced distortion is always at least 135 dB below the level of the music. The jitter-performance of
UltralLockDDS™ meets or exceeds the performance of Benchmark's UltraLock™ system, but does
not use asynchronous sample rate conversion (ASRC). The elimination of the ASRC processing
significantly reduces system latency and provides the most direct path from the A/D to the digital
interface.
Does my system have a jitter problem?
Jitter is present on every digital audio interface. This type of jitter is known as
interface jitter
and it
is present even in the most carefully designed audio systems. Interface jitter accumulates as digital
signals travel down a cable and from one digital device to the next. If we measure interface jitter in
a typical system we will find that it is 10 to 10,000 times higher than the level required for
accurate 24-bit conversion. However, this interface jitter has absolutely no effect on the audio
unless
it influences the conversion clock in an analog-to-digital converter (ADC) or in a digital-to-
analog converter (DAC).
Many converters use a single-stage Phase Lock Loop (PLL) circuit to derive their conversion clocks
from AES/EBU, Word Clock, or Super Clock reference signals. Single-stage PLL circuits provide
some jitter attenuation above 5 kHz but none below 5 kHz. Unfortunately, digital audio signals
often have their strongest jitter components at 2 kHz. Consequently, these converters can achieve
their rated performance only when driven from very low jitter sources and through very short
cables. It is highly unlikely that any converter with a single-stage PLL can achieve better than 16
bits of performance in a typical installation. Actual performance may be severely degraded below
specified performance in most installations.
Better converters usually use a two-stage PLL circuit to filter out more of the interface jitter. In
theory, a two-stage PLL can remove enough of the jitter to achieve accurate 24-bit conversion (and
some do). However, not all two-stage PLL circuits are created equal. Many two-stage PLLs do not
remove enough of the low-frequency jitter. In addition, two-stage PLL circuits often require many
