Becom TOREO-P650, Руководство пользователя по оборудованию

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Hardware User Manual - TOREO-P650
Last change: 6 September 2021/Version 1
4.3 Digital Inputs and Outputs
4.3.1 Input Stage
The implementation of the input stages for both digital inputs (reset and trigger) are shown in Figure 4-3.
Figure 4-3 Input Stage
The internal 10 k
Ω
pull-up resistor allows to assert the signals by just shorting the pin to the corresponding
reference ground. But also applying a voltage (limited to 36 V) to the pin is acceptable. The on/off threshold is
1.05 V.
4.3.2 Output Stage
The implementation of the output stages is shown in Figure 4-4.
Figure 4-4 Output Stage
The GPIOs 14 and 15 are routed to a dual solid-state relay (SSR) with one common pin. All three pins are
electrically isolated from the others on the M12 connector. The maximum current through each SSR is limited to
200 mA, the maximum allowed clamp voltage is 50 V.