BIOS settings
CB3067
73
Version: 1.0
BIOS entry
Options
PCI Express Root Port 9
Disabled / Enabled
Disable Gen2 Pll Shutdown and L1 and
Controller Power gating
Disabled / Enabled
Connection type
Built-in / Slot
Gen3 Eq Phase3 Method
Hardware / Static Coeff.
UPTP
None
DPTP
None
ACS
Enabled / Disabled
PTM
Enabled / Disabled
DPC
Enabled / Disabled
EDPC
Enabled / Disabled
URR
Disabled / Enabled
FER
Disabled / Enabled
NFER
Disabled / Enabled
CER
Disabled / Enabled
CTO
Disabled / Enabled
SEFE
Disabled / Enabled
SENFE
Disabled / Enabled
PME SCI
Enabled / Disabled
Hot Plug
Disabled / Enabled
Advanced Error Reporting
Enabled / Disabled
PCIe Speed
Auto / Gen1 / Gen2 / Gen3
Transmitter Half Swing
Disabled / Enabled
Detect Timeout
None
Extra Bus Reserved
None
Reserved Memory
None
Reserved I/O
None
PCH PCIe LTR Configuration
LTR
Enabled / Disabled
Snoop Latency Override
Disabled / Manual / Auto
Non Snoop Latency Override
Disabled / Manual / Auto
Force LTR Override
Disabled / Enabled
LTR Lock
Disabled / Enabled
Extra Options
NOTE
PCI Express Configuration
The BIOS entries and the options on ports 9 – 12 are identical. Port 9 is shown as an example.
Содержание CB3067
Страница 1: ...Original manual EN CB3067 Computerboard 12 10 2020 Version 1 0...
Страница 2: ......
Страница 97: ...Mechanical drawing CB3067 97 Version 1 0 9 2 PCB Holes Fig 19 CB3067 MZ MH...
Страница 99: ...Mechanical drawing CB3067 99 Version 1 0 Fig 22 CB3067 Cooling Bottom...
Страница 107: ......
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