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Camera Interface
2-12 BASLER A102
k
DRAFT
Operation in 3 x 8 Bit RGB Mode
A 3 x 8 bit RGB mode is available on
A102
kc
cameras. In 3 x 8 bit RGB mode, on each clock cycle,
the camera transmits 8 bits of red data, 8 bits of green data, and 8 bits of blue data for a single
pixel. A frame valid bit, a line valid bit and a data valid bit are also transmitted on each clock cycle.
The assignment of the bits is shown in Table 2-3. For more information about how the camera
determines the RGB values for each pixel, see Section
3.11 .
The pixel clock is used to time data sampling and transmission. As shown in Figure 2-4 and Figure
2-5, the camera samples and transmits data on each rising edge of the pixel clock.
The frame valid bit indicates that a valid frame is being transmitted. The line valid bit indicates that
a valid line is being transmitted. Pixel data is only valid when the frame valid bit and the line valid
bits are both high. The data valid bit is not used and should be ignored.
Video Data Sequence
When the camera is not transmitting valid data, the frame valid and the line valid bits sent on each
cycle of the pixel clock will be low. Once the camera has completed frame acquisition, it will begin
to send valid data:
• The frame valid bit will become high.
• On the pixel clock cycle where data transmission for line one begins, the line valid bit will
become high. Eight of the bits transmitted during this clock cycle will contain the red data for
pixel number one in line one, eight of the bits will contain the green data for pixel number one
in line one, and eight of the bits will contain the blue data for pixel number one in line one.
• On the next cycle of the pixel clock, the line valid bit will be high. Eight of the bits transmitted
during this clock cycle will contain the red data for pixel number two in line one, eight of the
bits will contain the green data for pixel number two in line one, and eight of the bits will con-
tain the blue data for pixel number two in line one.
• On the next cycle of the pixel clock, the line valid bit will be high. Eight of the bits transmitted
during this clock cycle will contain the red data for pixel number three in line one, eight of the
bits will contain the green data for pixel number three in line one, and eight of the bits will
contain the blue data for pixel number three in line one.
• This pattern will continue until all of the pixel data for line one has been transmitted.
• After all of the pixels in line one have been transmitted, the line valid bit will become low indi-
cating that valid data for line one is no longer being transmitted.
• On the pixel clock cycle where data transmission for line two begins, the line valid bit will
become high. Eight of the bits transmitted during this clock cycle will contain the red data for
pixel number one in line two, eight of the bits will contain the green data for pixel number one
in line two, and eight of the bits will contain the blue data for pixel number one in line two.
L
The data sequence outlined below, along with Figure 2-4 and Figure 2-5, describe
what is happening at the inputs to the Camera Link transmitter in the camera.
Note that the timing used for sampling the data at the Camera Link receiver in the
frame grabber varies from device to device. On some receivers, data must be sam-
pled on the rising edge of the pixel clock (receive clock), and on others, it must be
sampled on the falling edge. Also, some devices are available which allow you to
select either rising edge or falling edge sampling. Please consult the data sheet for
the receiver that you are using for specific timing information.