Horizontal Deflection
16
Date : 10/02/98
R7621085
R7621085
Technical description
voltage supplied from the +17VDC line . The drive signals are developed from the
17VDC and to prevent damage, due to insufficient drive, if this voltage becomes too
low, IC1 pin 3 gets low and inhibits the drive signal via the 'DEFL OFF'.
The DEFL OFF is connected with the R(eset) of the monoflop in IC1. The function
of the latter will be explained hereafter.
d) Input protection :
The H DR from the UN SYNC + VERT DEFL has as task to start and stop the
conduction of the Mosfets. If however the Mosfets are in conduction and there is a
"stop" that does not arrive, there is a risk of damaging the power switchers.
In such case, a stop pulse will be automatically generated by the monoflop in IC1,
output 7. This output remains low as low the input is retriggered at pin 5. When such
a trigger pulse is absent, the output switches high after a time determined by the
time constant R25 / C5 + current delivered by Q9. This current is tracked with the
line frequency by using the scan voltage as emitter supply. Note that a correction
on the base voltage occurs in the second range with Q58 on the subunit.
e) Horizontal scan failure.
Horizontal pulses are fed into the transistors Q17, Q21 and Q19. As long as there
are horizontal pulses on the base of these transistors, they are conducting for each
horizontal period, and the collectors are held "low" by C33, C44 and C37. These
smoothened collector voltages keep the gating diodes D28, D29 and D26 blocked.
If either one of the pulses or all pulses are missing, Q19 transistor gets in conduction
and turns its collector at low level. The SF line will be pulled low and the scan fail
condition will be met.
f) Inhibition of the scan at relay switching period.
The
HFM
(=Horizontal Frequency Mode)
voltage
(HIGH in the low freq. range and
LOW in the high freq. range) comes from the Sync+Vert Defl board . This voltage
is applied to IC2 pin 5 (on a level detector in IC2).
When HFM switches from HIGH to LOW (when the "high freq. range" is selected),
the output follows, and, a negative voltage transition occurs at the output . This
negative transition triggers the monoflop on the active low pin 5 input of the
monoflop IC1.
When on the other hand the freq. mode changes from Low to High, the positive
transition triggers now the monoflop at pin 4 (active high).
The end result is that for either transition, the output pin 6 will go "High". The time
that it will remain high is determined by the time constant C26/R25.
The "high" at pin 6 turns on the red LED D8 and it will stay on as long as pin 6 is
"high".
The second inverted output pin 7 (low pulse) turns off Q15. The collector of this
transistor DEFL ON is connected with the SMPS and as this an active LOW
output, the scan vHTHD is inhibited when this DEFL ON voltage is high (see
SMPS).
Therefore, the scan is inhibited, when Q15 is "OFF" during switching of the
frequency range.
Starting conditions
When the projector is first turned on, Q16 is forward biased due to the high charging
Содержание GRAPHICS 1209S
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