AZZA PT-5IH, Руководство по эксплуатации

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PT-5IH
SYSTEM BOARD
AWARD BIOS SETUP
5.6 CHIPSET FEATURES SETUP
ROM PCI / ISA BIOS (2A59FXXX)
CHIPSET FEATURES SETUP
AWARD SOFTWARE, INC.
Auto Configuration : Enabled DRAM ECC/PARITY Select : Parity
DRAM Timing : 70 ns Memory Parity/ECC Check : Disable
DRAM RAS# Precharge Time : 4 Single Bit Error Report : Enabled
DRAM R/W Leadoff Timing : 7/6 L2 Cache Cacheable Size : 64MB
DRAM RAS to CAS Delay : 3 Pipeline Cache Timing : Faster
DRAM Read Burst (EDO/FPM) : x333/x444
DRAM Write Burst Timing
: x333
Turbo Read Leadoff : Disabled
DRAM Speculative Leadoff : Disabled
Turn-Around Insertion : Disabled
ISA Clock : PCICLK/4
System BIOS Cacheable : Disabled
Video BIOS Cacheable : Disabled
8 Bit I/O Recovery Time : 1
16 Bit I/O Recovery Time : 1 ESC : Quit : Select Item
Memory Hole At 15M-16M : Disabled F1 : Help
PU/PD/+/- : Modify
Peer Concurrency : Enabled F5 : Old Values (Shift)F2 : Color
F6 : Load BIOS Default
F7 : Load Setup Default
Fig. 5-5 CHIPSET FEATURES SETUP screen.
WARNING : The CHIPSET FEATURES SETUP in this screen are provided so that technical
professionals can modify the Chipset to suit their requirement. If you are not a
technical engineer, do not use this program !
Auto Configuration :
When "Enabled", this parameter automatically enters and locks some of the optimum values for the chipset and
CPU. Otherwise, this parameter allows the values of these parameters could be changed.
DRAM Timing :
When "Auto Configuration" is "Enabled", this parameter provides two suit of the optimum values for the chipset
and CPU, depends on the DRAMs' speed, you can select "70 ns" or "60 ns", but the first value maybe caused
your system more stable.
DRAM ECC/PARITY Select / Memory Parity/ECC Check / Single Bit Error Report :
Please refer to page 4-1 for the rough description.
L2 Cache Cacheable Size :
Please refer to page 4-3 for the detailed description.
5-5