The
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P4X2-A MAINBOARD SERIES
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PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cy-
cles. Select Enabled to support compliance with PCI specification version 2.1.
3.5.4. Memory Hole
You can reserve this area of system memory for ISA adapter ROM. When this area is re-
served, it cannot be cached. The user information of peripherals that need to use this area
of system memory usually discusses their memory requirements.
3.5.5. System BIOS Cacheable
Selecting “Enabled” allows caching of the system BIOS ROM. This results system
performance. However, if any program writes to this memory area, a system error may
occur.
3.5.6. Video RAM Cacheable
Select Enabled allows caching of the video RAM, resulting in better system performance.
However, if any program writes to this memory area, a system error may occur.
3.6.1. VIA OnChip IDE Device
PC
B
I
O
S
PC
B
I
O
S
PC
B
I
O
S
PC
B
I
O
S
3.6. Integrated Peripherals
OnChip IDE Channel0
OnChip IDE Channel1
IDE Prefetch Mode
Primary Master PIO
Primary Slave PIO
Secondary MasterPIO
Secondary Slave PIO
Primary Master UDMA
Primary Slave UDMA
Secondary MasterUDMA
Secondary Slave UDMA
Item Help
Menu Level
!
!
!
!
CMOS Setup Utility - Copyright (C) 1984 - 2001 Award Software
VIA OnChip IDE Device
[Enabled]
[Enabled]
[Enabled]
[Auto]
[Auto]
[Auto]
[Auto]
[Auto]
[Auto]
[Auto]
[Auto]
CMOS Setup Utility - Copyright (C) 1984 - 2001 Award Software
Integrated Peripherals
!
!
!
!
VIA OnChip IDE Device
!
!
!
!
VIA OnChip PCI Device
!
!
!
!
SuperIO Device
Init Display First
OnChip USB Controller
USB Keyboard Support
IDE HDD Block Mode
SCR Port Address
SCR Port IRQ
Item Help
Menu Level
!
!
!
!
[Press Enter]
[Press Enter]
[Press Enter]
[PCI Slot]
[All Enabled]
[Disabled]
[Enabled]
[Disabled]
[11]
BIOS Management
