The
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Current FSB Frequency
The setting for this field will be automatically selected by the BIOS. The value that the BIOS
selects depends on the settings you have chosen for JP4. If you have a 100 MHz CPU but
have and set JP4 to OPEN the BIOS will detect 133 MHz.
Current Dram Frequency
The setting for this field will be automatically detected by the BIOS. The value that is se-
lected in derived from the RAM clock.
DRAM Clock
When you select
By SPD
The following menu will pop up:
100 MHz
133 MHz
By SPD
If you select
100 MHz
the DRAM clock speed will be PC1600 (100 MHz DDR). If you select
133 MHz
the DRAM clock speed will be PC2100 (133 MHz DDR). If you select
By SPD
the
BIOS will automatically detect the actual DRAM Clock.
DRAM Timing
This field determines the DRAM read/write timing. The performance parameters of the mem-
ory chips (DRAM) you have installed will determine the value in this field. Do not change the
value from the factory setting unless you install new memory that has a different perform-
ance rating than the original DRAMs.
SDRAM Cycle Length
Before SDRAM can execute a read command that it receives, there is a delay time, which is
measured in clock cycles (CLK). The lower the delay time the faster the execution of com-
mands will be. It is therefore desirable to minimize this cycle length. Some memory modules
are unable to deal with short delay times. We recommend that you set this delay time be-
tween 2.5 and 3 CLK’s (the default is 2.5). If your system becomes unstable we recommend
that you increase the delay time.
3.5.2. AGP & P2P Bridge Control
CMOS Setup Utility - Copyright ( C ) 1984 – 2001 Award Software.
AGP & P2P Bridge Control
AGP Aperture Size
AGP Mode
AGP Driving Control
X AGP Driving Value
AGP Fast Write
AGP Master 1 WS Write
AGP Master 1 WS Read
Item Help
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BIOS Management
