The
AZZA
P4X MAINBOARD SERIES
Page 32
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Current FSB Frequency
The setting for this field will be automatically selected by the BIOS.
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Current Dram Frequency
The setting for this field will be automatically detected by the BIOS. The
value that is selected in derived from the RAM clock.
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DRAM Clock
When you select By SPD The following menu will pop up:
100 MHz
133 MHz
By SPD
If you select 100 MHz the DRAM clock speed will be PC1600 (100 MHz DDR).
If you select 133 MHz the DRAM clock speed will be PC2100 (133 MHz
DDR). If you select By SPD the BIOS will automatically detect the actual
DRAM Clock.
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DRAM Timing
This field determines the DRAM read/write timing. The performance parame-
ters of the memory chips (DRAM) you have installed will determine the value
in this field. Do not change the value from the factory setting unless you in-
stall new memory that has a different performance rating than the original
DRAMs.
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SDRAM Cycle Length
Before SDRAM can execute a read command that it receives, there is a delay
time, which is measured in clock cycles (CLK). The lower the delay time the
faster the execution of commands will be. It is therefore desirable to mini-
mize this cycle length. Some memory modules are unable to deal with short
delay times. We recommend that you set this delay time between 2.5 and 3
CLK’s (the default is 2.5). If your system becomes unstable we recommend
that you increase the delay time.
AGP & P2P Bridge Control
AGP Aperture Size
[128M]
AGP Mode
[4X]
AGP Driving Control
[Auto]
X AGP Driving Value DA
AGP Fast Write
[Disabled]
AGP Master 1 WS Write
[Disabled]
AGP Master 1 WS Read
[Disabled]
Item Help
Menu Level
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CMOS Setup Utility - Copyright (C) 1984 - 2001 Award Software
AGP & P2P Bridge Control
Managing The PC BIOS
