SBC82810 Pentium
®
M All-in-One Half-Size Board User’s Manual
Award BIOS Utility
42
4.7 Advanced Chipset Features
Since the features in this section are related to the chipset on
the CPU board and are completely optimized, you are not
recommended to change the default settings in this setup table
unless you are well oriented with the chipset features.
CMOS Setup Utility-Copyright © 1984-2001 Award Software
Advanced Chipset Features
DRAM Timing
By SPD
Item Help
CASs Latency Time
2.5
Active to Recharge Delay
7
Menu Level
f
DRAM RAS# to CAS# Delay
3
DRAM RAS# Recharge
3
DRAM Data Integrity Mode
Non-ECC
MGM Core Frequency
Auto Max 400/333MHz
System BIOS Cacheable
Enable
Video BIOS Cacheable
Disabled
Memory Hole At 15M-16M
Disabled
Delayed Transaction
Disabled
Delay Prior to Thermal
16 Min
AGP Aperture Size (MB)
64
Init Display First
Onboard
** On-Chip VGA Setting **
On-Chip VGA
Enabled
On-Chip Frame Buffer Size
32MB
Boot Display
Auto
Panel Scaling
Auto
Panel Number
640 x480
ÇÈÆÅ
: Move Enter: Select +/-/PU/PD: Value F10: Save ESC: Exit F1: General Help
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
z
SDRAM CAS latency Time
You can select CAS latency time in HCLKs 2, 3, or Auto. The
board designer should set the values in this field, depending on
the DRAM installed. Do not change the values in this field unless
you change specifications of the installed DRAM or the installed
CPU.
z
DRAM Data Integrity Mode
This option sets the data integrity mode of the DRAM installed in
the system. The default setting is
“
Non-ECC
”
.
