AXIOMTEK SBC82610 SERIES, Руководство пользователя

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SBC82610 Half-size All-in-One CPU Card Series User’s Manual
Award BIOS Utility
43
DRAM Clock
This item allows you to select the DRAM clock value, depending on
whether the board has paged DRAMs or EDO (extended data output)
DRAMs. The available choices are 66 MHz and Host CLK.
SDRAM Cycle Length
When synchronous DRAM is installed, the number of clock cycles of CAS
latency depends on the DRAM timing. Do not reset this field from the
default value specified by the system designer. The default setting is
3 .
Memory Hole
To improve performance, certain space in memory is reserved for ISA
cards. This memory must be mapped into the memory space below
16MB. The available choices are 15M-16M and Disabled.
P2C/C2P Concurrency
This item allows you to enable/disable the PCI to CPU, CPU to PCI
concurrency. By default, this field is set to
Enabled .
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-
FFFFFh, resulting in better system performance. However, if any
program writes to this memory area, a system error may result.
The choice: Enabled, Disabled.
Video RAM Cacheable
Select Enabled allows caching of the A/B segment, resulting in better
system performance.
The Choice: Enabled, Disabled.
AGP Aperture Size
The field sets aperture size of the graphics. The aperture is a portion of
the PCI memory address range dedicated for graphics memory address
space. Host cycles that hit the aperture range are forwarded to the AGP
without any translation. The options available are 4M, 8M, 16M, 32M,
64M, 128M and 256M.
OnChip USB
This should be enabled if your system has a USB installed on the system
board and you wish to use it. Even when so equipped, if you add a higher
performance controller, you will need to disable this feature. The available
choices are Enabled and Disabled.