AXIOMTEK SBC82610 SERIES, Руководство пользователя

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SBC82610 Half-size All-in-One CPU Card Series User’s Manual
Award BIOS Utility
42
4.5 Advanced Chipset Features
Since the features in this section are related to the chipset on the
CPU board and are completely optimized, you are not recommended
to change the default settings in this setup table unless you are well
oriented with the chipset features.
Phoenix – AwardBIOS CMOS Setup Utility
Advanced Chipset Features
DRAM Timing By SPD Enabled Item Help
X DRAM Clock Host CLK
X SDRAM Cycle Length 3 Menu Level
X Bank Interleave Disabled
Memory Hole Disabled
P2C/C2P Concurrency Enabled
System BIOS Cacheable Disabled
Video RAM Cacheable Disabled
Frame Buffer Size 16M
AGP Aperture Size 64M
AGP-4X Mode Enabled
AGP Driving Control Auto
AGP Driving Value DA
OnChip USB Enabled
USB Keyboard Support Disabled
OnChip Sound Auto
OnChip Modem Disabled
CPU to PCI Write Buffer Enabled
PCI Dynamic Bursting Enabled
PCI Master 0 WS Write Enabled
PCI Delay Transaction Disabled
PCI#2 Access #1 Retry Enabled
AGP Master 1 WS Write Disabled
AGP Master 1 WS Read Disabled
: Move Enter: Select +/-/PU/PD: Value F10: Save ESC: Exit F1: General Help
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
DRAM Timing By SPD
This item allows you to select the value in this field, depending on
whether the board has paged DRAMs or EDO (extended data
output) DRAMs.