Avnet UltraZed Series, Схема подключения, Страница: 4 / 17

1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
CLOCK SYNTHESIZER & LVDS PORT
5P49V5935B521LTGI
CLKIN
1
CLKINB
2
V
D
D
A
5
CLKSEL
6
SD/OE
7
SEL1/SDA
8
SEL0/SCL
9
V
D
D
O
4
1
0
OUT4
11
OUT4B
12
OUT3B
13
OUT3
14
V
D
D
O
3
1
5
OUT2B
16
OUT2
17
V
D
D
O
2
1
8
OUT1B
19
OUT1
20
V
D
D
O
1
2
1
V
D
D
D
2
2
V
D
D
O
0
2
3
OUT0_SELB_I2C
24
EPAD
25
U1
Avnet Engineering Services
Project Name:
Size:
PCB Rev:
Sheet Title:
Date:
Sheet:
of
11/9/2016
4
SCH-US1CAR
1 02
Variant:
17
Doc Num:
04 - Clock & LVDS Port.SchDoc
B
UltraZed IO Carrier Card
Time:
1:51:52 PM
BOM:
01
CC_SDA 10[2B], 5[6C]
CC_SCL 10[3B], 5[6C]
GND
GTR_REFCLK3_P 10[2B]
GTR_REFCLK3_N 10[2B]
GTR_REFCLK0_P 10[3B]
GTR_REFCLK0_N 10[3B]
GTR_REFCLK1_P 10[2B]
GTR_REFCLK1_N 10[2B]
+VCCO_1V8
10.00K
R2
GND
FB1
10.00K
R5
10.00K
R6
C4
1uF C1
10uF
C2
0.1uF
GND
C3
0.1uF
C5
0.1uF
GND
Vddd Vdda
Vdda Vddd Vddd
1 2 3
5-146280-3
J1
SH1
1 2 3
5-146280-3
J2
SH2
SH3
1 2
5-146280-2
JP1
+VCCO_1V8
10.00K
R3
10.00K
R4
+VCCO_1V8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SH
21
SH
22
SH
23
SH
24
P1
TP_SCL
TP_SDA
TP_IRQ_N
TXS0104EPWR
A1
2
A2
3
A3
4
A4
5
B1
13
B2
12
B3
11
B4
10
GND
7
NC
6
NC
9
OE
8
VCCA
1
VCCB
14
U2
R10
4.75K
R11
0
R9
4.75K R8
4.75K R7
4.75K
C7
0.1uF
C6
0.1uF
+3.3V
+3.3V
JX2_HP_DP_24_P 9[4C]
JX2_HP_DP_24_N 9[4C]
JX2_HP_DP_28_P 9[4D]
JX2_HP_DP_28_N 9[4D]
JX2_HP_DP_25_P 9[5C]
JX2_HP_DP_25_N 9[5C]
JX2_HP_DP_29_P 9[5D]
JX2_HP_DP_29_N 9[5D]
JX2_HP_SE_04 9[4D]
+VCCO_1V8
+VCCO_1V8
+VCCO_1V8
1 3
BAT400D-7-F
D1
DNP
SH_GND4
0 R12
C8 0.1uF
LVDS CONNECTOR
IDT CLOCK SYNTHESIZER
2
R1
JX2_HP_DP_26_GC_P 9[4C]
JX2_HP_DP_26_GC_N 9[4D]
JX2_HP_DP_27_GC_P 9[5C]
JX2_HP_DP_27_GC_N 9[5C]
JX1_HP_DP_36_GC_P 9[1C]
JX1_HP_DP_36_GC_N 9[1C]
ADDR: 0xD4 - Default
ADDR: 0xD0 - Alternate
(TP_SCL)
(TP_SDA)
(TP_IRQ_N)
(TP_D0_P)
(TP_D0_N)
(TP_D1_P)
(TP_D1_N)
(TP_D2_P)
(TP_D2_N)
(TP_D3_P)
(TP_D3_N)
(TP_CLK_P)
(TP_CLK_N)
(USB3_P)
(USB3_N)
(SATA_P)
(SATA_N)
(DPORT_P)
(DPORT_N)
(PL_SYSCLK_P)
(PL_SYSCLK_N)
MODE 3: 52 MHz
}
MODE 3: 125 MHz
}
MODE 3: 27 MHz
}
MODE 3: 300 MHz
}
Layout Note:
Differential pairs:
Route at 100 ohms
Termination on JX3
connectors.
USER NOTE:
SEL [0:1] Mode (default):
JP1 installed, J1/J2 installed from
pins 1-2. This set's mode 3.
I2C Mode: JP1 not installed, J1/J2
installed
on pins 1-2.
Layout Note:
50 ohm single ohm.
100 ohm +/- 10% diff routing.