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6.4

USB

Ultra96-V1 provides one upstream (device) and two downstream (host) USB 3.0 connections. A
USB 2.0 downstream (host) interface is provided on the high speed expansion bus.

Two Microchip USB3320 USB 2.0 ULPI Transceivers and one Microchip USB5744 4-Port SS/HS
USB Controller Hub are specified.

Figure 3 below shows the Ultra96-V1 USB Setup.

USB 3.0

Downstream

Port A

USB 3.0

Downstream

Port B

USB 2.0

Downstream

Expansion Port

USB 3.0 Hub

USB5744

USB 3.0

Upstream

USB 3.0

Upstream

ULPI Phy

USB3320

ULPI Phy

USB3320

ZU3EG

UPLI0

ULPI1

GTR0

GTR1

USB 3.0 Connection

USB 2.0 Connecttion

Figure 3 – USB Setup

6.4.1

USB5744 Implementation Details

Refer to the USB5744 datasheet
(

http://ww1.microchip.com/downloads/en/DeviceDoc/00001855C.pdf

) and the EVB-USB5744

Evaluation Board schematics (

http://ww1.microchip.com/downloads/en/DeviceDoc/EVB-

USB5744_A1-sch.pdf

) for implementation details.

NOTE:

USB 3.0 Downstream Port A/B VUBS is controlled by a Microchip/Micrel MIC2009YML

USB Power Switch following the Evaluation Board implementation

NOTE:

USB2.0 Downstream Port VBUS is provided by the Low Speed Expansion Header 5V

supply (see 6.11.1). A Power switch is not required and the corresponding USB5744
PRT_CTLx pin for that port is left n/c.

Содержание Ultra96-V1

Страница 1: ...T Reach Further and the AV logo are registered trademarks of Avnet Inc All other brands are the property of their respective owners LIT Ultra96 HW User Guide rev 1 0 V1 1 Ultra96 V1 Single Board Computer Hardware User s Guide Version 1 1 ...

Страница 2: ...10 6 1 3 PS MIOs Banks 500 501 502 13 6 1 4 PS Bank 503 17 6 1 5 PS Bank 504 18 6 1 6 PS Bank 505 20 6 2 LPDDR4 Memory 21 6 3 microSD Card 21 6 4 USB 22 6 4 1 USB5744 Implementation Details 22 6 5 Wi Fi Bluetooth 23 6 5 1 Wi FI 23 6 5 2 Bluetooth 23 6 5 3 Bluetooth Audio 23 6 6 Mini DisplayPort 23 6 7 UART 23 6 8 I2C 24 6 9 User LEDs 24 6 10 MPSoC Thermal Bracket with Fan 24 6 11 Expansion Connect...

Страница 3: ...re User s Guide 1 0 07 Aug 2018 Updated release 1 1 25 Feb 2020 Added info regarding EOL 3 End of Life The original Ultra96 Single Board Computer was released in 2018 and shipped until April 2019 After that time it was replaced with an updated version called Ultra96 V2 To help with the nomenclature the original Ultra96 is now referred to as Ultra96 V1 The term Ultra96 may be used to refer to the f...

Страница 4: ...le logic that is not available from other 96Boards offerings Be a low cost starter kit for Zynq UltraScale MPSoC developers Showcase hardware acceleration for software bottlenecks Allow expansion to a variety of sensors and peripherals through the 96Boards mezzanine connectors Target applications for development including o Artificial Intelligence o Machine Learning o IoT Cloud connectivity for ad...

Страница 5: ...ltraScale MPSoC Overview 2 Zynq UltraScale MPSoC DC and AC Switching Characteristics 3 Zynq UltraScale MPSoC Technical Reference Manual 4 Zynq UltraScale MPSoC Packaging and Pinout Product Specification 5 Zynq UltraScale MPSoC PCB Design Guide 6 UltraScale Architecture SelectIO Resources 7 SBVA484 Package File 8 Xilinx Vivado Design Suite 9 Xilinx Software Development Kit 10 96Boards Specification...

Страница 6: ...MPSoC ZU3EG SBVA484 Storage o Micron 2 GB 512M x32 LPDDR4 Memory o MicroSD Socket Ships with Delkin Utility MLC Industrial 16GB card Wi Fi Bluetooth DisplayPort 1x USB 3 0 Type Micro B upstream port 2x USB 3 0 Type A downstream ports 40 pin Low speed expansion header 60 pin High speed expansion header Mounted on thermal bracket with fan Note that there is no on board wired Ethernet interface All c...

Страница 7: ...Page 7 5 2 Ultra96 V1 Block Diagram Figure 1 Ultra96 V1 Block Diagram ...

Страница 8: ...S I O UART CAN USB 2 0 I2C SPI 32b GPIO Real Time Clock WatchDog Timers Triple Timer Counters o High Speed Connectivity 4 PS GTR PCIe Gen1 2 Serial ATA 3 1 DisplayPort 1 2a USB 3 0 SGMII o Graphic Processing Unit ARM Mali 400 MP2 64KB L2 Cache Programmable Logic PL o System Logic Cells 154 350 o CLB Flip Flops 141 120 o CLB LUTs 70 560 o Distributed RAM Mb 1 8 o Block RAM Blocks 216 o Block RAM Mb...

Страница 9: ...Page 9 6 1 1 SBVA484 Package Figure 2 SBVA484 Package Diagram ...

Страница 10: ... 6 pins The PL I Os on Ultra96 V1 are tied to the Low Speed 96Boards Mezzanine the High Speed 96Boards Mezzanine Bluetooth and the fan Table 1 PL IO Bank 26 MPSoC Pin Number Bank MPSoC Site Name Function C8 26 IO_L8P_HDGC_AD4P_26 Bluetooth A8 IO_L10P_AD2P_26 A9 IO_L9N_AD3N_26 B9 IO_L9P_AD3P_26 B5 IO_L11N_AD1N_26 B7 IO_L12P_AD0P_26 E8 IO_L6P_HDGC_AD6P_26 HS Expansion D8 IO_L6N_HDGC_AD6N_26 D7 IO_L5...

Страница 11: ...N_T0L_N3_65 P3 IO_L2P_T0L_N2_65 U1 IO_L3N_T0L_N5_AD15N_65 U2 IO_L3P_T0L_N4_AD15P_65 H5 IO_L16N_T2U_N7_QBC_AD3N_65 J5 IO_L16P_T2U_N6_QBC_AD3P_65 F1 IO_L19N_T3L_N1_DBC_AD9N_65 G1 IO_L19P_T3L_N0_DBC_AD9P_65 E3 IO_L20N_T3L_N3_AD1N_65 E4 IO_L20P_T3L_N2_AD1P_65 D1 IO_L21N_T3L_N5_AD8N_65 E1 IO_L21P_T3L_N4_AD8P_65 C3 IO_L22N_T3U_N7_DBC_AD0N_65 D3 IO_L22P_T3U_N6_DBC_AD0P_65 C2 IO_L24N_T3U_N11_PERSTN0_65 D2...

Страница 12: ...10_AD6P_65 R1 IO_L5P_T0U_N8_AD14P_65 R4 IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65 R5 IO_L6N_T0U_N11_AD6N_65 T1 IO_L5N_T0U_N9_AD14N_65 T4 IO_L4N_T0U_N7_DBC_AD7N_65 P2 IO_T0U_N12_VRP_65 VRP Table 3 PL IO Bank 66 MPSoC Pin Number Bank MPSoC Site Name Function A2 66 IO_T3U_N12_66 HS Expansion A3 66 IO_L12N_T1U_N11_GC_66 NC A4 66 IO_L12P_T1U_N10_GC_66 B1 66 IO_L11N_T1U_N9_GC_66 B2 66 IO_L11P_T1U_N8_GC_66 B4 6...

Страница 13: ...E UART1 Header UART0 Bluetooth PL RTS CTS I2C1 I2C Hub SPI1 HS Expansion Header WE GPIO WiFi Enable BE GPIO Bluetooth Enable I2C GPIO I2C Hub Reset SD0 SD Card 3 3V level shifter LED GPIO User LEDs PB GPIO User Pushbutton USB GPIO USB Hub Vbus detect PI GPIO Power Pushbutton Controller INT_B PMU input DPAUX DiplayPort Auxiliary Signals INA GPIO INA226 PMBUS Alert PMU Input PMIC GPIO FPU PL power c...

Страница 14: ...SPI1 MIO9_SPI1_CS O Hi speed Expansion Header 10 MIO10_SPI1_MISO I 11 MIO11_SPI1_MOSI O 12 GPIO MIO12_I2C_MUX_RESET_B O I2C Mux reset 13 SD0 MIO13_SD0_DAT0 IO SDIO0 Data 0 14 MIO14_SD0_DAT1 IO SDIO0 Data 1 15 MIO15_SD0_DAT2 IO SDIO0 Data 2 16 MIO16_SD0_DAT3 IO SDIO0 Data 3 17 GPIO MIO17_PS_LED3 O User LED 3 18 MIO18_PS_LED2 O User LED 2 19 MIO19_PS_LED1 O User LED 1 20 MIO20_PS_LED0 O User LED 0 2...

Страница 15: ...ller Release enable output power off system 35 GPIO IO Test Point 36 GPIO MIO36_PS_GPIO1_0 IO Low speed Expansion GPIO C 37 GPIO MIO37_PS_GPIO1_1 IO Low speed Expansion GPIO D 38 SPI MIO38_SPI0_SCLK O SPI Serial Clock 39 GPIO MIO39_PS_GPIO1_2 IO Low speed Expansion GPIO E 40 GPIO MIO40_PS_GPIO1_3 IO Low speed Expansion GPIO F 41 SPI0 MIO41_SPI0_CS0 O SPI Chip Select 0 42 SPI0 MIO42_SPI0_MISO I SPI...

Страница 16: ...4 61 MIO61_USB0_DATA5 IO USB0 Data 5 62 MIO62_USB0_DATA6 IO USB0 Data 6 63 MIO63_USB0_DATA7 IO USB0 Data 7 64 USB1 MIO64_USB1_CLK I USB1 Clock 65 MIO65_USB1_DIR I USB1 Data bus direction 66 MIO66_USB1_DATA2 IO USB1 Data 2 67 MIO67_USB1_NXT I USB1 Data flow 68 MIO68_USB1_DATA0 IO USB1 Data 0 69 MIO69_USB1_DATA1 IO USB1 Data 1 70 MIO70_USB1_STP O USB1 Stop transfer 71 MIO71_USB1_DATA3 IO USB1 Data 3...

Страница 17: ...SJTAG error SRST and POR Table 8 PS Bank 503 MPSoC Pin Number Bank MPSoC Site Name K16 503 PS_ERROR_OUT_503 K18 PS_ERROR_STATUS_503 K15 PS_INIT_B_503 H15 PS_MODE1_503 J15 PS_MODE2_503 H18 PS_MODE3_503 H17 PS_PADI_503 J17 PS_PADO_503 K12 PS_POR_B_503 H14 PS_REF_CLK_503 K13 PS_SRST_B_503 ...

Страница 18: ...R_A11_504 AA18 PS_DDR_A12_504 AA19 PS_DDR_A13_504 AA17 PS_DDR_A14_504 AA16 PS_DDR_A15_504 W20 PS_DDR_CK_N0_504 V19 PS_DDR_CK_N1_504 V20 PS_DDR_CK0_504 V18 PS_DDR_CK1_504 U22 PS_DDR_CKE0_504 U21 PS_DDR_CKE1_504 V22 PS_DDR_CS_N0_504 U20 PS_DDR_CS_N1_504 AB9 PS_DDR_DM0_504 AB14 PS_DDR_DM1_504 U9 PS_DDR_DM2_504 W13 PS_DDR_DM3_504 AB11 PS_DDR_DQ0_504 Y10 PS_DDR_DQ1_504 AB10 PS_DDR_DQ2_504 W10 PS_DDR_DQ...

Страница 19: ...PS_DDR_DQ21_504 U10 PS_DDR_DQ22_504 T10 PS_DDR_DQ23_504 U11 PS_DDR_DQ24_504 U12 PS_DDR_DQ25_504 W12 PS_DDR_DQ26_504 W11 PS_DDR_DQ27_504 V14 PS_DDR_DQ28_504 U14 PS_DDR_DQ29_504 W15 PS_DDR_DQ30_504 V15 PS_DDR_DQ31_504 AA9 PS_DDR_DQS_N0_504 AA13 PS_DDR_DQS_N1_504 V8 PS_DDR_DQS_N2_504 V13 PS_DDR_DQS_N3_504 Y9 PS_DDR_DQS_P0_504 Y13 PS_DDR_DQS_P1_504 V9 PS_DDR_DQS_P2_504 V12 PS_DDR_DQS_P3_504 T18 PS_DDR...

Страница 20: ..._MGTRTXN0_505 K21 PS_MGTRTXP0_505 F22 PS_MGTRTXN1_505 F21 PS_MGTRTXP1_505 D22 PS_MGTRRXN2_505 D21 PS_MGTRRXP2_505 C20 PS_MGTRTXN2_505 C19 PS_MGTRTXP2_505 B22 PS_MGTRRXN3_505 B21 PS_MGTRRXP3_505 A20 PS_MGTRTXN3_505 A19 PS_MGTRTXP3_505 M20 PS_MGTRREF_505 E19 PS_MGTREFCLK3P_505 E20 PS_MGTREFCLK3N_505 G19 PS_MGTREFCLK2P_505 G20 PS_MGTREFCLK2N_505 H21 PS_MGTRRXP1_505 H22 PS_MGTRRXN1_505 M21 PS_MGTRRXP0...

Страница 21: ...inux boot The Delkin Part Number is S416APG49 U3000 3 rated at Read Performance 95MB s and Write Performance 55MB s measured using CrystalDiskMark There are several advantages to using MLC over the typical retail TLC that is readily available Table 11 Comparison of TLC vs MLC microSD Cards Retail TLC Delkin Utility MLC CrystalDiskMark Read Performance 80MB s 95 MB s CrystalDiskMark Write Performan...

Страница 22: ...USB3320 ZU3EG UPLI0 ULPI1 GTR0 GTR1 USB 3 0 Connection USB 2 0 Connecttion Figure 3 USB Setup 6 4 1 USB5744 Implementation Details Refer to the USB5744 datasheet http ww1 microchip com downloads en DeviceDoc 00001855C pdf and the EVB USB5744 Evaluation Board schematics http ww1 microchip com downloads en DeviceDoc EVB USB5744_A1 sch pdf for implementation details NOTE USB 3 0 Downstream Port A B V...

Страница 23: ...the PL the UART RX TX signals are connected to PS UART0 MIO2 MIO3 and the RTS CTS signals are connected to the PL High Density HD bank A blue LED is connected to BT_EN to indicate that Bluetooth is enabled 6 5 3 Bluetooth Audio WL183xMOD Bluetooth Audio connects through a PCM I2S interface Since MPSoC does not provide a PCM I2S interface this has to be implemented as a soft IP core in the PL The B...

Страница 24: ...C Thermal Bracket with Fan The Ultra96 V1 uses a thermal bracket with fan for the MPSoC device The bracket is mounted to the bottom side of the Ultra96 V1 to help dissipate heat A Sunon MC30060V1 000U A99 fan is used connected to 5V and GND at J18 and J19 Users can control the fan using signal FAN_PWM from PL IO F4 on Bank 65 6 11 Expansion Connectors 6 11 1 Low Speed Expansion Connector J7 Ultra9...

Страница 25: ...5 UART1_RxD 13 14 SPI0_DOUT PS_MIO43 PS_I2C0_SCL I2C0_SCL 15 16 PCM_FS HD_GPIO9 PS_I2C0_SDA I2C0_SDA 17 18 PCM_CLK HD_GPIO10 PS_I2C1_SCL I2C1_SCL 19 20 PCM_DO HD_GPIO11 PS_I2C1_SDA I2C1_SDA 21 22 PCM_DI HD_GPIO12 PS_MIO36 GPIO A 23 24 GPIO B PS_MIO37 PS_MIO39 GPIO C 25 26 GPIO D PS_MIO40 PS_MIO44 GPIO E 27 28 GPIO F PS_MIO45 HD_GPIO6 GPIO G 29 30 GPIO H HD_GPIO13 HD_GPIO7 GPIO I 31 32 GPIO J HD_GP...

Страница 26: ...I0_D0 HP_GPIO PS_SPI0_SCLK SD_SCLK SPI1_SCLK 9 10 CSI0 D0 HP_GPIO PS_SPI0_MISO SD_CMD SPI1_DIN 11 12 GND GND GND GND 13 14 CSI0_D1 HP_GPIO HD_GPIO_CC CLK0 CSI0_MCLK 15 16 CSI0_D1 HP_GPIO HD_GPIO_CC CLK1 CSI1_MCLK 17 18 GND GND GND GND 19 20 CSI0_D2 HP_GPIO HP_GPIO_CC DSI_CLK 21 22 CSI0_D2 HP_GPIO HP_GPIO_CC DSI_CLK 23 24 GND GND GND GND 25 26 CSI0_D3 HP_GPIO HP_GPIO DSI_D0 27 28 CSI0_D3 HP_GPIO HP...

Страница 27: ...lled to allow selecting the desired boot mode Figure 5 Boot Mode Switch SD Boot Mode Shown 7 2 JTAG Configuration and Debug JTAG access to the MPSoC is available through a 1x7 header J2 An external JTAG pod with flyleads or the Avnet Ultra96 JTAG UART Pod is required to interface to the board Figure 6 Ultra96 V1 JTAG Connection ...

Страница 28: ... outer diameter with 1 7mm center pin 4 75 1 7 for the power supply https en wikipedia org wiki EIAJ_connector However there is a bit of flexibility Avnet offers a 12V supply as an accessory part number AES ACC U96 4APWR with the following specifications Input AC 100 240v 50 60HZ Output DC 12V 4A 1 2m US AC cable with C8 socket 1 2m EU AC cable with C8 socket 1 2m UK AC cable with C8 socket 1 2m A...

Страница 29: ...shown below LPDDR4 CH PS VCC_PSINTLP VCC_PSAUX VCC_PSADC VCC_PSPLL VCC_PSINTFP VCC_PSINTFP_DDR VCCO_PSIOx VCCO_PSDDR VCC_PSDDR_PLL PS_MGTRAVCC PS_MGTRAVTT 0 85V 3 00A 5 VCC_PSINTFP PL VCCINT VCCAUX VCCAUX_IO VCCADC VCCOHD VCCBRAM VCCINT_IO 6V 18V 1 80V 500mA 3 VCC_PSAUX 1 10V 1 00A 5 VCCO_PSDDR 0 90V 300mA 3 MGTRAVCC 1 80V 50mA 3 MGTRAVTT 0 85V 3A 5 1 80V 500mA 5 VCCAUX VCCINT VCCOHP 1 20V 100mA 5...

Страница 30: ... MGTRAVCC BUCK6 VCC_PSAUX LDOA2 VCC_PSPLL BUCK4 VCC_3V3 BUCK3 VCCO_PSDDR 0 85 V 5 V 1 2 V 0 9 V 1 2 V 3 3 V 1 1 V 1 8 V 2 ms 4 ms GPO1 VCC_PSINTFP enable 2 ms 4 ms CTL5 PL_PWR_EN GPO4 VCCINT enable 4 ms SWB1_2 VCCAUX 1 8 V LDOA3 VCCO_HP 1 2 V CTL3 PS_LP_PWR_EN VSYS 5 6V LDO5V LDO3P3 I2 C Available LDOA1 MGTRAVTT 1 8 V GPO3 PS_POR_B 2 ms 2 ms 2 ms 2 5 ms CTL1 PS_POR_PB_B 2 5 ms 2 ms ...

Страница 31: ...is required Avnet has many avenues to search depending on your needs For general question regarding Ultra96 V1 please visit our website at Error Hyperlink reference not valid http avnet me ultra96 v1 Here you can find documentation technical specifications videos and tutorials reference designs and other support Detailed questions regarding Ultra96 V1 hardware design software application developme...

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