MSC Q7-MB-EP6
User Manual
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3.15
SPI Interface, Bios disable/Alternative Boot (X1001, J1001)
References:
Type:
Weitronic 137-10-3-60-1-2-10
Mating:
female crimp-connector Reference FCI 65043-032
Pin Signal
(Rev1)* Pin Signal
(Rev1)*
1
SPI_CS0#
(MISO)
2
+3V3
(BIOS_DIS#)
3
SPI_MISO
(MOSI)
4
HOLD#
(10k pull-up
3V3)
(CS0#)
5
WP#
(10k pull-up 3V3)
(SCK)
6
SPI_SCK
(CS1#)
7
GND
(n.c.)
8
SPI_MOSI
(n.c.)
9
BIOS_DISABLE#/BOOTALT#
(GND)
10 SPI_CS1#
(+3V3)
Table 27
Pinout SPI X1001
NOTE:
(Rev1)* Pinout at the Rev1 engineering samples (LY10B90401)
NOTE:
Depending on the Qseven
TM
module used, it may not be possible to use a normal cable to
connect to the SPI signals on the pin header. Some modules use a high speed buffer for
driving this signal, so high speed signal routing considerations should be taken into
consideration, when connecting to the SPI interface. Please refer to the module user manual
for more details or contact Technical Support.
Function
1-2
BIOS_DISABLE# / BOOT_ALT# Low
2-3
BIOS_DISABLE# / BOOT_ALT# High
removed
(default)
BIOS_DISABLE# / BOOT_ALT#
Table 28
Jumper J1001 Serial Selection
3.16
LPC Interface / GPIOs (X1005)
The EP6 baseboard provides the LPC signals from the Qseven
TM
connector, multiplexed with
general purpose input/output pins.
References:
Type:
Weitronic 137-10-3-60-1-2-10
Mating:
female crimp-connector Reference FCI 65043-032
Pin
Signal
Pin
Signal
1
LPCCLK / GPIO4
2
SERIRQ / GPIO6
3
LPCAD0 / GPIO0
4
LPFRAME# / GPIO5
5
LPCAD1 / GPIO1
6
LPCLDRQ# / GPIO7
7
LPCAD2 / GPIO2
8
GND
9
LPCAD3 / GPIO3
10
+3V3
Table 29
Pinout LPC X1005
