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It is recommended that any custom interface to be implemented be run through the Vivado tool
suite for a sanity check on place and route and timing closure in advance of end user carrier card
manufacturing.
Pin out details of the available PL IO are included in section 2.8: Expansion Headers.
2.6 Clock Source
The PicoZed 7010/7020 connects a dedicated 33.3333 MHz clock source to the Zynq-7000 AP
SoC
’s PS. An ABRACON ASDMB-33.333MHZ-LC-T or similar oscillator with 40-ohm series
termination is used. The PS infrastructure can generate up to four PLL-based clocks for the PL
system
.
2.7 Reset Sources
2.7.1
Zynq Power
‐
on Reset (PS_POR_B)
The Zynq PS supports an external power-on reset signal. The power-on reset is the master reset
of the entire chip. This signal resets every register in the device capable of being reset. On
PicoZed 7010/7020 this signal is labeled PG_MODULE and it is connected to the power good
output of the final stage of the power regulation circuitry. These power supplies have open drain
outputs that pull this signal low until the output voltage is valid. If an expansion card is connected
to PicoZed 7010/7020, the expansion card should also wire-OR to this net and not release it until
the expansion card power is also good. Review the PicoZed 7010/7020 schematic for other
devices that are reset by the PG_MODULE open drain signal.
To stall Zynq boot-up, this signal should be held low. No other signal (PS_SRST_B,
PROGRAM_B, or INIT_B) is capable of doing this as in other Xilinx FPGA architectures.
2.7.2
PROGRAM_B, DONE, PUDC_B, INIT_B Pins
INIT_B, PROGRAM_B and PUDC_B all have pull-up resistors to appropriate voltages applied to
them. The INIT_B, PUDC_B and DONE signals are routed to the carrier card via the Micro
Headers, JX1 and JX2.
There is not a DONE LED indicator on the PicoZed 7010/7020 System-On-Module. When PL
configuration is complete DONE will go high. It is recommended that the DONE signal be
connected to an LED on the carrier card to indicate when the FPGA configuration is complete.
When mating to the Avnet PicoZed FMC Carrier Card a blue LED labeled DONE will illuminate.
2.7.3
Processor Subsystem Reset
System reset, labeled PS_SRST_B, resets the processor as well as erases all debug
configurations. The external system reset allows the user to reset all of the functional logic within
the device without disturbing the debug environment. For example, the previous break points set
by the user remain valid after system reset. Due to security concerns, system reset erases all
memory content within the PS, including the OCM. The PL is also reset in system reset. System
reset does not re-sample the boot mode strapping pins.
This active-low signal can be asserted via the carrier card through the Micro Header interface.
Note: This signal cannot be asserted while the boot ROM is executing following a POR reset. If
PS_SRST_B is asserted while the boot ROM is running through a POR reset sequence it will
trigger a lock-down event preventing the boot ROM from completing. To recover from lockdown
the device either needs to be power cycled or PS_POR_B needs to be asserted.
