RTX-24EM
User guide
The technical characteristics can change without notice. AUR°EL S.p.A doesn’t assume the responsibility to the damages caused by an improper use of the device.
AUR°EL S.p.A.
Via Foro dei Tigli, 4 - 47015 Modigliana (FC) – ITALY 12/11/2019 - Rev. B
Tel.: +390546941124 – Fax: +390546941660 Page 28
http://www.aurel.it
Note 1
: Reception mode is operated by the internal microcontroller, which operates by taking control of
RAM2
and
RXFIFO
. Read and Write SPI accesses to
RAM2
will put the microcontroller on hold. If the SPI
transaction time is too long (if SCK frequency is close to channel data rate), correct reception operation can
be corrupted.SPI commands to retrieve
RAM2
values such as
Limit_RSSI[3:0]
or
DFT_Mes[7:0]
should be
sent immediately after IRQ signal has gone high.
11.2 Reception flow, mode payload size defined in RAM2
This section describes the entire flow for receiving RF data, in mode payload size defined in RAM2, starting
from the RTX-24EM in power down mode (ENABLE (Pin 10) or nRESET (Pin 4) = GND).
The steps are the same as described in section 11.1 excepted:
•
the payload size
N_Pay[4:0]
must be write in
RAM2
after step 12;
•
the header byte no longer defines the number of byte of the payload;
•
the
ROM_Boot_Address
must be set
= 128
for High sensitivity mode or
192
for Normal sensitivity
mode, in step 22.
