Atmel XMEGA B, Руководство пользователя

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250 XMEGA B [DATASHEET]
8291B–AVR–01/2013

Bit 4
–
RXACK: Received Acknowledge
This flag contains the most recently received acknowledge bit from the slave. This is a read-only flag. When read as zero,
the most recent acknowledge bit from the slave was ACK, and when read as one the most recent acknowledge bit was
NACK.

Bit 3
–
ARBLOST: Arbitration Lost
This flag is set if arbitration is lost while transmitting a high data bit or a NACK bit, or while issuing a START or repeated
START condition on the bus. Writing a one to this bit location will clear ARBLOST.
Writing the ADDR register will automatically clear ARBLOST.

Bit 2
–
BUSERR: Bus Error
This flag is set if an illegal bus condition has occurred. An illegal bus condition occurs if a repeated START or a STOP
condition is detected, and the number of received or transmitted bits from the previous START condition is not a multiple
of nine. Writing a one to this bit location will clear BUSERR.
Writing the ADDR register will automatically clear BUSERR.
 Bit 1:0
–
BUSSTATE[1:0]: Bus State
These bits indicate the current TWI bus state as defined in Table 19-6 . The change of bus state is dependent on bus
activity. Refer to the “TWI Bus State Logic” on page 241 .
Table 19-6. TWI master bus state.
Writing 01 to the BUSSTATE bits forces the bus state logic into the idle state. The bus state logic cannot be forced into
any other state. When the master is disabled, and after reset, the bus state logic is disabled and the bus state is
unknown.
19.9.5 BAUD
–
Baud Rate register
The baud rate (BAUD) register defines the relation between the system clock and the TWI bus clock (SCL) frequency.
The frequency relation can be expressed by using the following equation:
[1]
The BAUD register must be set to a value that results in a TWI bus clock frequency (f
TWI
) equal or less than 100kHz or
400kHz, depending on which standard the application should comply with. The following equation [2] expresses equation
[1] solved for the BAUD value:
BUSSTATE[1:0] Group Configuration Description
00 UNKNOWN Unknown bus state
01 IDLE Idle bus state
10 OWNER Owner bus state
11 BUSY Busy bus state
Bit 7 6 5 4 3 2 1 0
+0x04
BAUD[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
f
TWI
f
sys
2(5 BAUD
 
) +
---------------------------------------[Hz] =