Atmel XMEGA B, Руководство пользователя

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217 XMEGA B [DATASHEET]
8291B–AVR–01/2013
18.8 Auto Zero Length Packet
Some IN transfer requires a zero length packet to be generated in order to signal end of transfer to the host. The auto
zero length packet (AZLP) function can be enabled to perform this generation automatically, thus removing the need for
application software or CPU intervention to perform this task.
18.9 Transaction Complete FIFO
The transaction complete FIFO provides a convenient way to keep track of the endpoints that have completed IN or OUT
transactions and need firmware intervention. It creates a first-come, first-served work queue for the application software.
The FIFO size is (MAXEP[3:0] + 1) × 4 bytes, and grows downward, starting from EPPTR - 1. This SRAM memory is
allocated only when the FIFO is enabled.
Figure 18-10.Transfer complete FIFO.
To manage the FIFO, a five-bit write pointer (FIFOWP) and five-bit read pointer (FIFORP) are used by the USB module
and application software, respectively. FIFORP and FIFOWP are one's complemented, and thus hold negative values.
The SRAM location of the data is the sum of EPPTR and the read or write pointer. The number of items in the FIFO is the
difference between FIFOWP and FIFORP. For the programmer, the FIFORP and FIFOWP values have to be cast to a
signed 8-bit integer, and then the offset into the FIFO from this signed integer must be deducted.
The transaction complete interrupt flag (TRNIF) in the INFLAGSB[CLR,SET] register is set to indicate a non-empty FIFO
when FIFORP != FIFOWP, cleared when they are equal, and also set when the FIFO is full.
Each time an endpoint IN or OUT transaction completes successfully, its endpoint configuration table address is stored in
the FIFO at the current write pointer position (i.e., EPPTR + 2 × FIFOWP) and FIFOWP is decremented. When the
pointer reaches the FIFO size, it wraps to zero. When application software reads FIFORP, this is decremented in the
same way. Reading the write pointer has no effect. The endpoint configuration table address can then be read directly
from (EPPTR + 2 × FIFORP).
Figure 18-11.USB transaction complete FIFO example.
USB_ TC_ FIFO
TC_EP_ ADDRH_0
TC_EP_ ADDRL_0
TC_ EP_ ADDRH_ MAX
ENDPOINT DESCRIPTOR TABLE
TC_ EP_ ADDRH_1
TC_EP_ ADDRL_1
INTERNAL SRAM
TC_ EP_ ADDRH_2
TC_ EP_ ADDRH_2
FIFOWP
FIFORP
EPPTR
SRAM
ADDRESS
EPPTR –
4x( MAXEP+1)
Ep X
t
Ep Y Ep Z
FIFO
X
Y
Z
FIFOWP
FIFORP
X
Y
Z
FIFOWP
FIFORP
FIFO
X
Y
FIFOWP
FIFORP
FIFO
X
FIFOWP
FIFORP
FIFO
FIFOWP FIFORP