43
AT94KAL Series FPSLIC
Rev. 1138G–FPSLI–11/03
General-purpose
Register File
Figure 28 shows the structure of the 32 x 8 general-purpose working registers in the CPU.
Figure 28.
AVR CPU General-purpose Working Registers
All the register operating instructions in the instruction set have direct- and single-cycle access
to all registers. The only exception is the five constant arithmetic and logic instructions SBCI,
SUBI, CPI, ANDI and ORI between a constant and a register and the LDI instruction for load-
immediate constant data. These instructions apply to the second half of the registers in the
register file – R16..R31. The general SBC, SUB, CP, AND and OR and all other operations
between two registers or on a single-register apply to the entire register file.
As shown in Figure 28 each register is also assigned a data memory address, mapping the
registers directly into the first 32 locations of the user Data Space. Although not being physi-
cally implemented as SRAM locations, this memory organization provides great flexibility in
access of the registers, as the X, Y and Z registers can be set to index any register in the file.
The 4 to 16
Kbytes
of data SRAM, as configured during FPSLIC download, are available for
general data are implemented starting at address $0060 as follows:
Addresses beyond the maximum amount of data SRAM are unavailable for write or read and
will return unknown data if accessed. Ghost memory is not implemented.
7
0
Addr.
R0 $00
R1
$01
R2
$02
. . .
R13
$0D
General-purpose
Working Registers
R14
$0E
R15
$0F
R16
$10
R17
$11
. . .
R26
$1A
AVR X-register Low Byte
R27
$1B
AVR X-register High Byte
R28
$1C
AVR Y-register Low Byte
R29
$1D
AVR Y-register High Byte
R30
$1E
AVR Z-register Low Byte
R31
$1F
AVR Z-register High Byte
4 Kbytes
$0060 : $0FFF
8 Kbytes
$0060 : $1FFF
12 Kbytes
$0060 : $2FFF
16 Kbytes
$0060 : $3FFF