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Circuit Description
5-2
AT91EB01 Evaluation Board User Manual
5.6
JTAG Interface,
Reset, Interrupts
& LEDs
An ARM-standard 20-pin box header (J2) is provided to enable connection of an
EmbeddedICE interface (using an EmbeddedICE to Multi-ICE adapter) or Multi-ICE
interface to the JTAG inputs on the AT91. This allows code to be developed on the
board without the use of system resources such as memory and serial ports.
The IRQ, FIQ and TIOB0 switches are debounced and buffered. A supervisory circuit
has been included in the design to detect and consequently reset the board when the
3.3V supply voltage drops below 3.08V. It also provides a debounced reset signal.
The schematic also shows LEDs 1, 2 and 3 which are for general purpose use and are
connected to timer (or I/O) pins TIOA0/P1, TIOA1/P4 and TIOB0/P2.
5.7
Serial Interface
Two 9-way D-type connectors (J5/6) are provided for serial port connection. Serial port
A (J5) is used primarily for Host PC communication and is a DB9 Female connector.
TXD and RXD are swapped so that a straight through cable can be used. CTS and RTS
are connected together as is DCD, DSR and DTR.
Serial port B (J6) is a DB9 male connector with TXD and RXD obeying the standard RS-
232 pinout. Apart from TXD, RXD and ground, the other pins are not connected.
RS-232 level conversion is provided by a MAX3223 device (U13) and associated bulk
storage capacitors.
5.8
Layout Drawing
The layout diagram schematic shows an approximate floorplan for the board. This has
been designed to give the lowest board area, whilst still providing access to all
testpoints, links and switches on the board.
The size is approximately 4.5 inches square with four mounting holes, one at each cor-
ner, into which feet are attached. The board has two signal layers and two power
planes.
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