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AT91EB01 Evaluation Board User Manual
5-1
Section 5
Circuit Description
5.1
AT91EB01 Top
Level
The top level schematic in “Appendix B - Schematics” on page 7-1 shows the blocks in
the system. Each block is described in the appropriate section below.
5.2
AT91M40400
Processor
This schematic shows the AT91M40400. The footprint is for a 100-pin TQFP package.
Wirelink (WL2) can be removed by the user to allow measurement of the current
demand by the microcontroller.
5.3
I/O Expansion
The I/O Expansion connector makes available to the user the General Purpose I/O
(GPIO) lines, VDD and Ground. Surface mount links 5, 6, 7, 8 and 9 are used to select
between the I/O lines being used by the evaluation board or by the user via the I/O
expansion connector. The connector is not fitted at the factory; however, the user can fit
any 17 x 2 connector on a 0.1" (2.54 mm) pitch.
5.4
External Bus
Interface
This schematic shows one AT29LV1024-15JC 128K bytes 16-bit Flash and four
512K x 8 SRAM devices.
Note:
The AT91EB01 is fitted with four 128K x 8 SRAM devices.
The schematic also shows the Bus Expansion connector which, like the I/O Expansion
connector, is not fitted at the factory. The user can fit any 32 x 2 connector on a 0.1"
(2.54 mm) pitch to gain access to the data, address, chip select, read/write, oscillator
output, and wait state pins. Pin 8 on this connector can be used to apply an external
clock frequency to the board assuming the clock select jumper is fitted accordingly (see
Appendix A). VDD and Ground are also available on the connector.
Switch 1 shown on this schematic is used to select either Read only access of all loca-
tions in Flash or allow Read/Write access to the top 64K bytes. This is to prevent the
Angel Debug Program which is stored in the lower 64K bytes from being erased.
5.5
Power, Crystal
Oscillator and
Clock
Distribution
The system clock is derived from a single 32.768 MHz crystal oscillator. This is divided
by a 4-bit binary counter to give alternate clock frequencies of 32.768 MHz divided by 2,
4 or 8. The system clock frequency is selected by fitting a jumper link in one position of
the link field (LK2) and details of this can be found in Appendix A. One position in LK2
selects an external oscillator to be applied via the Expansion Bus Interface.
The Voltage Regulator provides 3.3V to the board and will light the red POWER LED
when operating. Power can be applied via the 2.1 mm connector to the regulator in
either polarity because of the diode rectifying circuit. The regulators can tolerate supply
transients to 30V although they will shut down without damage if they overheat.
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