PXIe-3352 User Manual
Publication No. 981049 Rev. B
Overview and Features 1-4
Astronics Test Systems
through a Rb87 resonance cell, and finally detected by a photo-diode detector.
The resonance cell is located inside the microwave cavity.
A Step Recovery Diode (SRD), located in the cavity generates a nominal
frequency of 90 MHz.
When this frequency deviates from the precise Rb87 resonance frequency, the
photo-diode senses a change in the light transmitted through the resonance cell.
This change is amplified by the preamplifier and used to control the OCXO.
The atomic resonance frequency, however, is sensitive to external magnetic fields.
Therefore, a double magnetic shield is used to attenuate external fields by a factor
of about 5000. The “CField” coils set the magnetic field. Controlling the current
via this coil enables the analog frequency adjustments that were described before.
When GPS satellites are not available, the system performance reverts to that of a
stand-alone Rubidium. (This period is called the Holdover Period.)
RS232 Interface
The Rubidium block also includes electronics boards that control the unit’s
operation and RS232 interface to communicate with electronics outside of the unit.
GPS Block
The GPS block is a self-contained high performance Global Position System
receiver. It can simultaneously acquire on 66 channels and track on up to 22
channels. The main purpose of the GPS block is to provide a GPS based 1 PPS
output to train and discipline the Rubidium oscillator. This technique results in
improved long-term stability comparable to that of a Cesium-frequency standard.
The GPS block requires a 3.3 VDC lithium battery in order to retain the positioning
lock data during power down. Without a 3.3 VDC lithium battery present, the GPS
cannot function.
Control of the Rubidium oscillator is available to enable or disable outputs or to
query it for information such as serial number, operating hours, operating
temperature, event history, self-test, and other performance indicators.
PXIe and Digital Interface
The PXIe interface allows the FPGA to communicate data and commands
between the PXIe chassis and the PXIe-3352. The FPGA then translates the data
and commands via 9600 baud rate TTL serial to the GPS IC and via 9600 baud
rate RS-232 to the Rubidium block.
