ASROCK Rack C422 WSI/IPMI, Руководство пользователя

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PCIE PLL ORT
Overshoot Reduction Technology improves the BCLK signal to decrease overshoot/
undershoot. Default is Level 1.
CPU Output Divider
The default is set to 2 where the max BCLK is 1000 MHz, while divider 4 lowers the
max BCLK to 500 MHz, while divider 10 lowers the max BCLK to 200 MHz, and
divider 1 turns it into 2000 NHz.
SRC Output Divider
The default is set to 2 where the max BCLK is 1000 MHz, while divider 4 lowers the
max BCLK to 500 MHz, while divider 10 lowers the max BCLK to 200 MHz, and
divider 1 turns it into 2000 NHz.
PCIE Output Divider
The default is set to 2 where the max BCLK is 1000 MHz, while divider 4 lowers the
max BCLK to 500 MHz, while divider 10 lowers the max BCLK to 200 MHz, and
divider 1 turns it into 2000 NHz.
SRC0 Source
Choose to select the SRC0 source from CPU PLL or PCIE PLL.
CPU2/SRC1 Source
Choose to select the CPU2/SRC1 source from CPU PLL or PCIE PLL.
ClockGen Delay
Delay at beginning of ClockGen; delay Value * 1ms.
BCLK Strap
Choose to select corresponding straps for BCLK.
Boot Performance Mode
Select the performance state that the BIOS will set before OS handoff.
Intel Turbo Boost Technology
Intel Turbo Boost Technology enables the processor to run above its base operating
frequency when the operating system requests the highest performance state.