AsahiKASEI AK4493, Руководство пользователя

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[AK4493]
017012230-E-00 2017/12
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(2) I
2
C-bus Control Mode
(I2C pin = “H”)
The AK4493 supports the fast-mode I
2
C-bus (max: 400kHz, Ver. 1.0).
(2)-1. WRITE Operation
Figure 68 shows the data transfer sequence for the I
2
C-bus mode. All commands are preceded by a
START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START
condition (
Figure 74 ). After the START condition, a slave address is sent. This address is 7 bits long
followed by the eighth bit that is a data direction bit (R/W). The most significant five bits of the slave
address are fixed as “00100”. The next bits are CAD1 and CAD0 (device address bits). This bit identifies
the specific device on the bus. The hard-wired input pin (CAD1 pin, CAD0 pin) sets these device address
bits (
Figure 69 ). If the slave address matches that of the AK4493, the AK4493 generates an acknowledge
and the operation is executed. The master must generate the acknowledge-related clock pulse and
release the SDA line (HIGH) during the acknowledge clock pulse (
Figure 75
). A R/W bit value of “1”
indicates that the read operation is to be executed, and “0” indicates that the write operation is to be
executed.
The second byte consists of the control register address of the AK4493 and the format is MSB first. The
most significant three bits are fixed as
“000” (
Figure 70 ). The data after the second byte contains control
data. The format is MSB first, 8bits ( Figure 71 ). The AK4493 generates an acknowledge after each byte is
received. Data transfer is always terminated by a STOP condition generated by the master. A LOW to
HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (
Figure 74 ).
The AK4493 can perform more than one byte write operation per sequence. After receipt of the third byte
the AK4493 generates an acknowledge and awaits the next data. The master can transmit more than one
byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data
packet the internal address counter is incremented by one, and the next data is automatically taken into
the next address. If the address exceeds
“15H” prior to generating a stop condition, the address counter
will “roll over” to “00H” and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. HIGH or LOW state of
the data line can only be changed when the clock signal on the SCL line is LOW (
Figure 76 ) except for the
START and STOP conditions.
SDA
S
T
A
R
T
A
C
K A
C
K
S
Slave
Address
A
C
K
Sub
Address(n)
Data(n) P
S
T
O
P
Data(n+x)
A
C
K
Data(n+1)
A
C
K
R/W=
“0”
A
C
K
Figure 68. Data Transfer Sequence in I
2
C Bus Mode
0 0 1 0 0 CAD1 CAD0 R/W
(CAD0 is set by pin)
Figure 69. The First Byte
0 0 0 A4 A3 A2 A1 A0
Figure 70. The Second Byte
D7 D6 D5 D4 D3 D2 D1 D0
Figure 71. Byte Structure after The Second Byte