[AK4458]
014011794-E-01
2015/08
- 28 -
2. Auto Setting Mode (ACKS bit = “1”)
MCLK frequency and the sampling speed are detected automatically (
Table 5
) and DFS2-0 bits are ignored.
The MCLK frequency corresponding to each sampling speed should be provided externally (
Table 6
,
Table 7
).
MCLK
Sampling Speed
1152fs
Normal (fs
32kHz)
512fs/256fs 768fs/384fs
Normal
256fs
384fs
Double
128fs
192fs
Quad
64fs
96fs
Oct
32fs
48fs
Hex
Table 5. Sampling Speed (Auto Setting Mode)
LRCK
MCLK(MHz)
Sampling
Speed
fs
32fs
48fs
64fs
96fs
128fs
32.0kHz
N/A
N/A
N/A
N/A
N/A
Normal
44.1kHz
N/A
N/A
N/A
N/A
N/A
48.0kHz
N/A
N/A
N/A
N/A
N/A
88.2kHz
N/A
N/A
N/A
N/A
N/A
Double
96.0kHz
N/A
N/A
N/A
N/A
N/A
176.4kHz
N/A
N/A
N/A
N/A
22.5792
Quad
192.0kHz
N/A
N/A
N/A
N/A
24.5760
Quad
384kHz
N/A
N/A
24.576 36.864
N/A
Oct
768kHz
24.576
36.864
N/A
N/A
N/A
Hex
Table 6. System Clock Example (Auto Setting Mode)
LRCK
MCLK(MHz)
Sampling
Speed
fs
192fs
256fs
384fs
512fs
768fs
1152fs
32.0kHz
N/A
8.1920
12.2880
16.3840 24.5760
36.8640
Normal
44.1kHz
N/A
11.2896
16.9344
22.5792 33.8688
N/A
48.0kHz
N/A
12.2880
18.4320
24.5760 36.8640
N/A
88.2kHz
N/A
22.5792
33.8688
N/A
N/A
N/A
Double
96.0kHz
N/A
24.5760
36.8640
N/A
N/A
N/A
176.4kHz
33.8688
N/A
N/A
N/A
N/A
N/A
Quad
192.0kHz
36.8640
N/A
N/A
N/A
N/A
N/A
Quad
384kHz
N/A
N/A
N/A
N/A
N/A
N/A
Oct
768kHz
N/A
N/A
N/A
N/A
N/A
N/A
Hex
Table 7. System Clock Example (Auto Setting Mode)
MCLK= 256fs/384fs supports sampling rate of 8kHz~96kHz (
Table 8
). However, when the sampling rate is
8kHz~48kHz, DR and S/N will degrade by approximately 3dB as compared to when MCLK= 512fs/768fs.
ACKS pin
MCLK
DR,S/N
L
256fs/384fs/512fs/768fs
115dB
H
256fs/384fs
112dB
H
512fs/768fs
115dB
Table 8. Relationship of DR, S/N and MCLK frequency (fs = 44.1kHz)
