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Asahi KASEI AK4458, Общее описание устройства

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Asahi KASEI AK4458 Скачать руководство пользователя страница 21

 

 

[AK4458] 

014011794-E-01 

2015/08 

- 21 - 

 (Ta=-40 

 105

C; AVDD=3.0 

 5.5V, TVDD=1.62 

 1.98V / 3.0 

 3.6V) 

Parameter 

Symbol 

Min. 

Typ. 

Max. 

Unit 

Control Interface Timing (3-wire Serial mode): 

CCLK Period 
CCLK Pulse Width Low 

Pulse Width High 

CDTI Setup Time 
CDTI Hold Time 
CSN “H” Time 

CSN “

” to CCLK “

” 

CCLK “

” to CSN “

” 

 

tCCK 

tCCKL 

tCCKH 

tCDS 

tCDH 

tCSW 

tCSS 

tCSH 

 

200 

80 
80 
40 
40 

150 

50 
50 

 

 
 
 
 
 
 
 
 
 

 

nsec 
nsec 
nsec 
nsec 
nsec 
nsec 
nsec 
nsec 

Control Interface Timing (I

2

C Bus mode): 

SCL Clock Frequency 
Bus Free Time Between Transmissions 
Start Condition Hold Time (prior to first clock pulse) 
Clock Low Time 
Clock High Time 
Setup Time for Repeated Start Condition 
SDA Hold Time from SCL Falling                (

Note 30

) 

SDA Setup Time from SCL Rising 
Rise Time of Both SDA and SCL Lines 
Fall Time of Both SDA and SCL Lines 
Setup Time for Stop Condition 
Pulse Width of Spike Noise Suppressed by Input Filter 
Capacitive load on bus 

 

fSCL 

tBUF 

tHD:STA 

tLOW 

tHIGH 

tSU:STA 

tHD:DAT 

tSU:DAT 

tR 

tF 

tSU:STO 

tSP 

Cb 

 

- 

1.3 
0.6 
1.3 
0.6 
0.6 

0 

0.1 

- 
- 

0.6 

0 

- 

 

 

400 

- 
- 
- 
- 
- 
- 
- 

1.0 
0.3 

- 

50 

400 

 

kHz 

sec 

sec 

sec 

sec 

sec 

sec 

sec 

sec 

sec 

sec 

nsec 

pF

 

Power-down & Reset Timing

                          (

Note 31

)

 

PDN Accept Pulse Width 
PDN Reject Pulse Width 

 

 

tAPD 
tRPD 

 

150 

 
 

 
 

30 

 

nsec 
nsec 

Note 30. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. 
Note 31.The AK4458 can be reset by setting the PDN pin to “L” upon power-up. The PDN pin must held “L” 

for more than 150ns for a certain reset. The AK4458 is not reset by the “L” pulse less than 30ns. 

Note 32. I

2

C is a trademark of NXP B.V.

Содержание AK4458

Страница 1: ...und Plate Bars Car Audios Automotive External Amplifiers Measuring Instruments and Control Systems 2 Features 1 DR S N 115dB 2 THD N 107dB 3 256x Over sampling OSR Doubler 4 Sampling Rate 8kHz 768kHz...

Страница 2: ...AK4458 014011794 E 01 2015 08 2 16 Digital Input Level CMOS 17 Power Supply TVDD 1 7 3 6V AVDD 3 0 5 5V 18 Supporting 105 C Temperature Exposed pad is connected to ground 19 Package 48 pin QFN...

Страница 3: ...18 Timing Diagram 22 9 Functional Descriptions 26 D A Conversion Mode PCM mode DSD mode 26 System Clock 26 Audio Interface Format 30 D A Conversion Mode PCM Mode DSD Mode Switching Timing 43 Digital...

Страница 4: ...AK4458 014011794 E 01 2015 08 4 11 Package 82 Outline Dimensions 82 Material Lead finish 82 Marking 83 12 Revision History 83 IMPORTANT NOTICE 84...

Страница 5: ...polator SCF SCF Vref Bias I2C AOUTR3N VREFH3 VREFL3 AOUTL3P AOUTL3N AOUTR3P 8X Interpolator SCF SCF AOUTR4N VREFH4 VREFL4 AOUTL4P AOUTL4N AOUTR4P Vref 8X Interpolator SCF SCF Vref SDTI3 DSDR2 TDMO1 SD...

Страница 6: ...er sample 1fs rate data to 8fs rate Modulator Output multi bit data to SCF This block consists of a third order digital delta sigma modulator Noise Rejection Filter Attenuate out of band noise to prev...

Страница 7: ...SDTI1 DSDR1 5 SDTI2 DSDL2 6 SDTI3 DSDR2 TDMO1 7 SDTI4 DSDL3 TDMO2 8 DSDR3 20 19 18 17 16 15 14 13 SCL CCLK TDM1 CAD0_I2C CSN DIF I2C PS CAD0_SPI AOUTL1N AOUTL1P AOUTR3N VREFL3 VREFH3 AOUTL3N AVSS AOU...

Страница 8: ...s changed to H soft mute cycle is initiated When it is returning to L the output mute is released 12 CAD1 I Chip Address 0 Pin in I2 C Bus or 3 wire serial control mode Hi Z DCHAIN I Daisy Chain Mode...

Страница 9: ...sitive Voltage Reference Input Pin AVDD Hi Z 41 VREFL4 I Negative Voltage Reference Input Pin AVSS Hi Z 42 AOUTR4N O Rch Negative Analog Output 4 Pin Hi Z 43 AOUTR4P O Rch Positive Analog Output 4 Pin...

Страница 10: ...ay result in permanent damage to the device Normal operation is not guaranteed at these extremes 7 Recommended Operation Conditions AVSS DVSS 0V Note 5 Parameter Symbol Min Typ Max Unit Power Supplies...

Страница 11: ...60dBFS 107 52 100 dB dB fs 96kHz BW 40kHz 0dBFS 60dBFS 104 48 dB dB fs 192kHz BW 40kHz BW 80kHz 0dBFS 60dBFS 60dBFS 104 48 44 dB dB dB Dynamic Range 60dBFS with A weighted Note 10 110 115 dB S N A we...

Страница 12: ...mA Power down PDN pin L Note 15 AVDD TVDD 1 100 A Note 9 Measured by Audio Precision System Two Averaging mode Note 10 Figure 75 External LPF Circuit Example 1 100dB for 16 bit data Note 11 Figure 75...

Страница 13: ...1 fs Frequency Response Note 19 0 07dB 0 43 5 kHz Digital Filter SCF Note 19 Frequency Response 0 40 0kHz 0 3 0 1 dB Sharp Roll Off Filter Characteristics fs 192kHz Ta 40 105 C AVDD 3 0 5 5V TVDD 1 7...

Страница 14: ...Unit Digital Filter Pass band Note 20 0 05dB PB 0 17 7 kHz 3 0dB PB 39 5 kHz Pass band Ripple Note 17 PR 0 043 0 043 dB Stop band Note 20 SB 85 3 Stop band Attenuation Note 19 SA 73 dB Group Delay Not...

Страница 15: ...Mode DEM OFF SLOW bit 0 SD bit 1 Parameter Symbol Min Typ Max Unit Digital Filter Pass band Note 16 0 05dB PB 0 43 5 kHz 3 0dB PB 46 8 kHz Pass band Ripple Note 17 PR 0 0031 0 0031 dB Stop band Note...

Страница 16: ...ol Min Typ Max Unit Digital Filter Pass band Note 21 0 05dB PB 0 24 2 kHz 3 0dB PB 42 1 kHz Pass band Ripple Note 17 PR 0 05 0 05 dB Stop band Note 21 SB 83 0 43 5 Stop band Attenuation Note 19 SA 82...

Страница 17: ...rom 25 to 75 Peak levels of DSD signal above this duty are not recommended by SACD format book Scarlet Book Note 23 It is assumed that the output level is 0dB when the input signal is 1kHz and the dut...

Страница 18: ...fsq tLRH tLRL 8 54 108 1 128fs 1 128fs 54 108 216 kHz kHz kHz nsec ns TDM256 mode TDM1 0 bits 10 Normal Speed Mode High time Double Speed Mode High time Low time fsn fsd tLRH tLRL 8 54 1 256fs 1 256f...

Страница 19: ...Note 26 BICK Pulse Width Low BICK Pulse Width High BICK to LRCK Edge Note 25 LRCK Edge to BICK Note 25 TDMO1 2 Setup time BICK TDMO1 2 Hold time BICK Note 28 SDTI1 2 Hold Time SDTI1 2 Setup Time tBCK...

Страница 20: ...DCLK Pulse Width High DCLK Edge to DSDL R Note 29 tDCK tDCKL tDCKH tDDD 36 36 5 1 256fs 5 nsec nsec nsec nsec Note 24 When the 1152fs 512fs or 768fs 256fs or 384fs 128fs or 192fs are switched the AK4...

Страница 21: ...Falling Note 30 SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise Suppressed by Input Filt...

Страница 22: ...tLRB LRCK VIH BICK VIL TDMO 50 TVDD tBSS VIH VIL tBLR tSDS SDTI VIH VIL tSDH tBSH Figure 3 Audio Interface Timing PCM mode 1 fCLK tCLKL VIH tCLKH MCLK VIL dCLK tCLKH x fCLK tCLKL x fCLK 1 fs VIH LRCK...

Страница 23: ...tDCKL tDCK tDDD VIH DSDL1 4 DSDR1 4 VIL Figure 4 Audio Serial Interface Timing DSD Normal Mode DCKB bit 0 VIH DCLK VIL tDDD VIH DSDL1 4 DSDR1 4 VIL tDCKH tDCKL tDCK tDDD tDDD VIH DSDL1 4 DSDR1 4 VIL...

Страница 24: ...CSN VIH CCLK VIL VIH CDTI VIL VIH VIL C1 C0 R W A4 tCCKL tCCKH tCDS tCDH Figure 6 WRITE Command Input Timing 3 wire Serial mode CSN VIH CCLK VIL VIH CDTI VIL VIH VIL D3 D2 D1 D0 tCSW tCSH Figure 7 WRI...

Страница 25: ...tLOW tBUF tHD STA tR tF tHD DAT tSU DAT tSU STA Stop Start Start Stop tSU STO VIL VIH VIL tSP Figure 8 I2 C Bus mode Timing tAPD tRPD PDN VIL tCSS CSN VIH CCLK VIL VIH CDTI VIL VIH VIL C1 C0 R W A4 tA...

Страница 26: ...ntrol System Clock 1 PCM Mode The external clocks which are required to operate the AK4458 are MCLK BICK and LRCK MCLK should be synchronized with LRCK but the phase is not critical The MCLK is used t...

Страница 27: ...s 32 0kHz N A N A N A N A N A N A Normal 44 1kHz N A N A N A N A N A N A 48 0kHz N A N A N A N A N A N A 88 2kHz N A N A N A N A N A N A Double 96 0kHz N A N A N A N A N A N A 176 4kHz N A N A N A N A...

Страница 28: ...6 36 864 N A Oct 768kHz 24 576 36 864 N A N A N A Hex Table 6 System Clock Example Auto Setting Mode LRCK MCLK MHz Sampling Speed fs 192fs 256fs 384fs 512fs 768fs 1152fs 32 0kHz N A 8 1920 12 2880 16...

Страница 29: ...Mode The AK4458 supports 64fs 128fs and 256fs data stream fs 32kHz 44 1kHz 48kHz DSDSEL1 0 bits control this setting Table 10 DSDSEL1 DSDSEL0 DSD data stream fs 32kHz fs 44 1kHz fs 48kHz 0 0 2 048MHz...

Страница 30: ...pins using BICK and LRCK inputs Data is selected by SDS2 0 bits The data input to the SDTI3 4 pins are ignored BICK is fixed to 128fs Six data formats are supported and selected by the DIF2 0 bits as...

Страница 31: ...SB justified 128fs 12 1 1 0 32 bit MSB justified 128fs 13 1 1 1 32 bit I2 S compatible 128fs TDM256 1 0 0 0 0 N A 256fs 0 0 1 N A 256fs 14 0 1 0 24 bit MSB justified 256fs 15 0 1 1 24 bit I2 S compati...

Страница 32: ...3 2 1 0 Lch Data Rch Data Figure 10 Mode 0 Timing SDTI1 4 LRCK BICK 64fs 0 9 1 10 11 12 31 0 1 9 10 11 12 31 0 1 19 0 19 0 Mode 1 Don t care Don t care 19 MSB 0 LSB SDTI1 4 Mode 4 23 MSB 0 LSB 20 19 0...

Страница 33: ...1 0 Don t care 23 23 Figure 13 Mode 3 Timing LRCK BICK 64fs SDTI1 4 0 22 1 2 24 31 0 1 31 0 1 32 MSB 0 LSB 30 1 0 31 Lch Data Rch Data 23 30 22 2 24 23 30 30 1 0 31 30 31 Mode 5 6 Figure 14 Mode 5 6...

Страница 34: ...31 31 30 31 Mode11 12 Figure 16 Mode 8 11 12 Timing LRCK BICK 128fs 128 BICK L1 32 BICK R1 32 BICK L2 32 BICK R2 32 BICK SDTI1 2 22 0 22 0 22 0 22 0 23 23 23 23 23 SDTI1 2 Mode9 Mode13 30 0 30 0 30 2...

Страница 35: ...igure 19 Mode 14 17 18 Timing LRCK BICK 256fs 23 0 L1 32 BICK 256 BICK 23 0 R1 32 BICK 23 23 0 L2 32 BICK 23 0 R2 32 BICK SDTI1 Mode15 31 0 31 30 31 0 30 31 0 30 31 0 30 SDTI1 Mode19 23 0 L3 32 BICK 2...

Страница 36: ...1 LRCK 512BICK 22 0 23 22 0 23 22 0 23 22 0 23 22 2 0 23 22 0 23 22 0 23 22 0 23 SDTI1 Mode25 L1 32 BICK R1 32 BICK L2 32 BICK R2 32 BICK L3 32 BICK R3 32 BICK L4 32 BICK R4 32 BICK 32 BICK 32 BICK 32...

Страница 37: ...R1 L1 SDTI2 R2 L2 SDTI3 R3 L3 SDTI4 R4 L4 Figure 25 Data Slot in Normal Mode SDTI1 R1 L1 SDTI2 LRCK 128 BICK R2 L2 R3 L3 R4 L4 Figure 26 Data Slot in TDM128 Mode SDTI1 R1 L1 LRCK 256 BICK R2 L2 R3 L3...

Страница 38: ...L2 R2 TDM256 0 0 0 L1 R1 L2 R2 L3 R3 L4 R4 0 0 1 L2 R2 L3 R3 L4 R4 L5 R5 0 1 0 L3 R3 L4 R4 L5 R5 L6 R6 0 1 1 L4 R4 L5 R5 L6 R6 L7 R7 1 0 0 L5 R5 L6 R6 L7 R7 L8 R8 1 0 1 L6 R6 L7 R7 L8 R8 L1 R1 1 1 0 L...

Страница 39: ...t AK4458 s SDTI1 pin TDMO1 is 8ch shifted data of SDTI1 At TDM512 mode TDMO2 outputs L Figure 30 shows data I O example of TDM512 mode SDTI1 L5 8 R5 8 data is the input for the DAC of the second AK445...

Страница 40: ...e 32 Second AK4458 Third AK4458 DSP SDTI1 TDMO1 SDTI1 TDMO1 SDTI2 TDMO2 SDTI2 TDMO2 DVSS First AK4458 SDTI1 TDMO1 SDTI2 TDMO2 Figure 31 Daisy Chain for Three Devices TDM512 Mode SDTI1 DSP LRCK 512 BIC...

Страница 41: ...y shifting 4ch The first AK4458 accepts SDTI1 L1 2 R1 2 and SDTI2 L5 6 R5 6 data as input data of DAC DIF2 0 bits setting of both first AK4458 and the second AK4458 must be the same First AK4458 Secon...

Страница 42: ...nd Phase Modulation mode Figure 36 Input data is clocked in on a rising or falling edge of DCLK that is set by DCKB bit The frequency of DCLK is variable at 64fs 128fs and 256fs by setting DSDSEL1 0 b...

Страница 43: ...Data PCM Mode DSD Mode Figure 37 D A Mode Switching Timing PCM to DSD RSTN bit D A Data D A Mode 5 fs DSD Data PCM Data DSD Mode PCM Mode Figure 38 D A Mode Switching Timing DSD to PCM Note 35 The sig...

Страница 44: ...ff Filter Table 16 Digital Filter Setting Do not care The slowest frequency characteristics setting is when SSLOW bit 1 De emphasis Filter PCM mode A digital de emphasis filter is available for 32kHz...

Страница 45: ...e transition between set values is a soft transition in Mode0 1 2 3 eliminating switching noise in the transition The register settings are maintained when switching the mode between PCM and DSD modes...

Страница 46: ...1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 default 001 1 1 4 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 010 2 1 4 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 2 0...

Страница 47: ...AK4458 014011794 E 01 2015 08 47 Figure 41 Mode2 FIR Filter Except DSD direct mode Figure 42 Mode3 FIR Filter Except DSD direct mode Figure 43 Mode4 FIR Filter Except DSD direct mode...

Страница 48: ...AK4458 014011794 E 01 2015 08 48 Figure 44 Mode5 FIR Filter Except DSD direct mode Figure 45 Mode6 FIR Filter Except DSD direct mode Figure 46 Mode7 FIR Filter Except DSD direct mode...

Страница 49: ...AK4458 014011794 E 01 2015 08 49 Figure 47 Mode0 FIR Filter DSD Direct Mode Figure 48 Mode1 FIR Filter DSD Direct Mode Figure 49 Mode2 FIR Filter DSD Direct Mode...

Страница 50: ...AK4458 014011794 E 01 2015 08 50 Figure 50 Mode3 FIR Filter DSD Direct Mode Figure 51 Mode4 FIR Filter DSD Direct Mode Figure 52 Mode5 FIR Filter DSD Direct Mode...

Страница 51: ...AK4458 014011794 E 01 2015 08 51 Figure 53 Mode6 FIR Filter DSD Direct Mode Figure 54 Mode7 FIR Filter Except DSD Direct Mode...

Страница 52: ...4 bits does not detect zero Zero detect All zero detection channels set by L1 4 bits and R1 4 bits detect zero Table 21 DZF Pin Function LR Channel Output Signal Select PCM mode DSD mode Input and out...

Страница 53: ...ert 1 1 L2ch In Invert L2ch In Invert 1 1 0 0 R2ch In R2ch In 1 0 R2ch In Invert R2ch In 0 1 R2ch In R2ch In Invert 1 1 R2ch In Invert R2ch In Invert Table 23 Output Select for DAC2 MONO3 bit SELLR3 b...

Страница 54: ...rt L4 0 1 R4 L4 Invert 1 1 R4 Invert L4 Invert 1 0 0 0 L4 L4 1 0 L4 Invert L4 0 1 L4 L4 Invert 1 1 L4 Invert L4 Invert 1 1 0 0 R4 R4 1 0 R4 Invert R4 0 1 R4 R4 Invert 1 1 R4 Invert R4 Invert Table 25...

Страница 55: ...ing condition to normal operation mode from full scale detection status is selected by DMC bit if DDM bit 1 When DMC bit 0 the AK4458 will return to normal operation automatically by inputting a norma...

Страница 56: ...evel by the same cycle The soft mute is effective for changing the signal source without stopping the signal transmission SMUTE pin or SMUTE bit Attenuation DZF pin ATT_Level AOUT 8192 fs GD GD 1 2 3...

Страница 57: ...ition 1 Internal Reference Voltage Error Internal reference voltage is not powered up 2 LDO Over Voltage Detection LDO voltage 2 2 2 5V 3 LDO Over Current Detection LDO current 40 110mA Table 28 Error...

Страница 58: ...cillator 10ms max If the LDOE pin L the shutdown switch is activated after the AK4458 is powered up The internal circuits will be powered up in 1msec max after the activation of the shutdown switch Du...

Страница 59: ...FH 2 VREFH 2 VREFH 2 Table 29 Power Off and Reset Function 1 Power OFF Function 1 PW1 4 bits All DAC1 4 can be powered down immediately by setting PW1 4 bits to 0000 In this time all circuits except r...

Страница 60: ...Internal RSTN bit 2 3 fs 5 3 4 fs 6 Don t care Notes 1 The analog output corresponding to digital input has group delay GD 2 Analog outputs are floating Hi Z in power down mode 3 Small pop noise occu...

Страница 61: ...Normal Operation GD GD D A Out Analog D A In Digital Clock In MCLK 2 3 External MUTE 5 2 MCLK Stop RSTN bit Power down Power down 4 4 4 Hi Z 5 1 PDN pin 5 Notes 1 After the AK4458 is powered up the P...

Страница 62: ...8192 times if SYNCE bit is set to 1 during operation in PCM mode or when RSTN bit is set to 0 Example In the case of using the AK4458 with the AK4452 Figure 62 The AK4452 and the AK4458 have synchroni...

Страница 63: ...not available in parallel mode All functions controlled exclusively by Serial mode are only available in their default register settings TDM1 pin TDM0 pin DIF pin Mode 0 0 0 Mode6 Table 13 0 0 1 Mode7...

Страница 64: ...MHz max The internal registers are initialized by setting the PDN pin L In serial mode an internal timing circuit is reset by setting RSTN bit 0 but register values are not initialized CDTI CCLK CSN C...

Страница 65: ...tains control data The format is MSB first 8bits Figure 67 The AK4458 generates an acknowledge after each byte is received Data transfer is always terminated by a STOP condition generated by the maste...

Страница 66: ...al address counter and increments the internal address counter by 1 If the master does not generate an acknowledge but generates a stop condition instead the AK4458 ceases transmission SDA Slave Addre...

Страница 67: ...Conditions SCL FROM MASTER acknowledge DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER 1 9 8 START CONDITION not acknowledge clock pulse for acknowledgement S 2 Figure 71 Acknowledge on the I2 C B...

Страница 68: ...e Y Short delay Filter Enable Y De emphasis Response OFF 01H 0AH 0EH DEM3 0 Y Soft Mute Enable Normal Operation 01H SMUTE Y Y DSD PCM Mode Select PCM mode 02H D P Y Y Master Clock Frequency Select at...

Страница 69: ...PW2 PW1 DEM21 DEM20 0BH Control 7 ATS1 ATS0 0 SDS0 PW4 PW3 DCHAIN 0 0CH Control 8 INVR4 INVL4 INVR3 INVL3 0 FIR2 FIR1 FIR0 0DH Control 9 MONO4 MONO3 MONO2 0 SELLR4 SELLR3 0 0 0EH Control 10 DEM41 DEM...

Страница 70: ...ck Frequency Auto Setting Mode Enable PCM only 0 Disable Manual Setting Mode default 1 Enable Auto Setting Mode When ACKS bit 1 the sampling frequency and MCLK frequency are detected automatically Add...

Страница 71: ...ection MONO1 DAC1 enters monaural output mode when MONO bit 1 Table 22 0 Stereo mode default 1 MONO mode DCKB Polarity of DCLK DSD Only 0 DSD data is output from DCLK falling edge default 1 DSD data i...

Страница 72: ...bits default 1 Super Slow Roll off Mode DFS2 Sampling Speed Control Table 2 Default value is 0 Normal Speed See also register address 01H for DFS1 0 A click noise occurs when switching DFS2 0 bits se...

Страница 73: ...nly valid when DDM bit 1 and DMC bit 1 It releases a mute state when DSD data is muted by DDM and DMC bits DMC DSD mute control 0 Auto Return default 1 Mute Hold This register is only valid when DDM b...

Страница 74: ...SYNC Mode Disable 1 SYNC Mode Enable default L3 4 R3 4 Zero Detect Flag Enable Bit for the DZF pin 0 Disable default 1 Enable Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 08H Sound Control L1 R1 L2 R2 0...

Страница 75: ...the DSDR2 4 L2 4 pins are full scale Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0AH Control 6 TDM1 TDM0 SDS1 SDS2 PW2 PW1 DEM21 DEM20 R W R W R W R W R W R W R W R W R W Default 0 0 0 0 1 1 0 1 DEM21...

Страница 76: ...C3 0 DAC3 power OFF 1 DAC3 power ON default SDS2 0 DAC1 4 Data Select 0 Normal Operation 1 Output Other Slot Data Table 14 ATS1 0 DAC Digital attenuator transition time setting Table 19 Default value...

Страница 77: ...0 Stereo mode default 1 MONO mode Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0EH Control 10 DEM41 DEM40 DEM31 DEM30 0 0 0 0 R W R W R W R W R W R W R W R W R W Default 0 1 0 1 0 0 0 0 DEM31 0 DAC3 De...

Страница 78: ...P AOUT1LN VREFL1 VREFH1 AOUTR1N AOUTR1P 34 VREFH3 33 AOUTL3N 32 AOUTL3P 31 AVDD 30 AVSS 29 AOUTR2P N 28 AOUTR2N 27 VREFH2 26 VREFL2 25 AOUTL2N DVSS 46 TVDD 45 LDOE 44 AOUTR4P 43 AOUTR4N 42 VREFL4 41 V...

Страница 79: ...AOUTR2P N 28 AOUTR2N 27 VREFH2 26 VREFL2 25 AOUTL2N DVSS 46 TVDD 45 LDOE 44 AOUTR4P 43 AOUTR4N 42 VREFL4 41 VREFH4 40 AOUTL4N 39 AOUTL4P 38 AOUTR3P 37 CAD1 12 24 AOUTL2P 36 AOUTR3N PDN 48 1u 10u 0 1u...

Страница 80: ...igh frequency should be placed as near as possible to the supply pin 2 Voltage Reference The potential difference between the VREFH1 2 3 4 pin and the VREFL1 2 3 4 pin sets the analog output range The...

Страница 81: ...itive full scale when the duty is 100 all 1 and the output level is negative full scale when the duty is 0 all 0 In ideal case a 0V voltage is output when the input signal duty is 50 The internal swit...

Страница 82: ...AK4458 014011794 E 01 2015 08 82 11 Package Outline Dimensions Material Lead finish Package molding compound Epoxy Lead frame material Cu Lead frame surface treatment Solder Pb free plate...

Страница 83: ...Filter fs 96kHz DF SCF FR 0 40kHz max 0 1dB Description Addition 13 to 16 Description of Pass band spec of 3 0dB was added Description Delete 13 to 16 Frequency Response of 3 0 6 0 dB was deleted Des...

Страница 84: ...AKM in writing 3 Though AKM works continually to improve the Product s quality and reliability you are responsible for complying with safety standards and for providing adequate designs and safeguard...

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