Artesyn Embedded Technology ATCA-7370, Инструкция по установке и эксплуатации

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Maps and Registers
ATCA-7370/ATCA-7370-S Installation and Use (6806800P54G)
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6.2.1 Register Decoding
The FPGA registers may be accessed from the host or the IPMI. For the host, the LPC bus
interface is used. The IPMC uses an SPI interface.
<reset>: 0 or 1 Default value after deassertion of the reset signal <reset>.
Ext. External Reset Source. Default depends on external logic level.
Table 6-7 Register Access Type
Access Description
r Read only
w Write only
r/w Read and write
w1c Write-1-to-clear, ignore bit while reading
r/w1c Read and write-1-to-clear, write 0 has no effect
r/w1s Read and write-1-to-set, write 0 has no effect
r/w1t Read and write-1-to-toggle, write 0 has no effect
LPC: The prefix "LPC:" signals that the access is restricted to the LPC
interface.
E. g.: LPC: r/w means that
the register bit is
read/writable from the
LPC interface
IPMC: The prefix "IPMC:" signals that the access is restricted to the IPMC
SPI interface.
E. g.: IPMC: r/w means
that the register bit is
read/writable from IPMC
SPI interface
Table 6-6 Register Default (continued)
Default Description