CY8CKIT-049-4xxx PSoC® 4 Prototyping Kit Guide, Doc. #: 001-90711 Rev. *J
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Hardware
4.3.3.1
Functionality of the J1 and J2 Headers (PSoC 4)
The main PSoC 4 board contains two dual-inline headers (J1 and J2). These headers are both
1×22-pin headers and include all of the I/O available on the PSoC 4 devices. These headers support
all of the available ports, GND, VDD, and connections to passive elements and user-input devices.
The J1 and J2 headers support 100-mil spacing, so you can solder the male connectors to connect
the CY8CKIT-049-4xxx to any development breadboard.
Figure 4-4. J1 and J2 Headers
Table 4-1. J1 Header Pin Details
PSoC 4 GPIO Header (J1)
Pin
Signal
Description
J1_01
P4.0
GPIO
J1_02
P4.1
GPIO
J1_03
P4.2
GPIO/CMOD
J1_04
P4.3
GPIO/CTANK
J1_05
P0.0
GPIO
J1_06
P0.1
GPIO
J1_07
P0.2
GPIO
J1_08
P0.3
GPIO
J1_09
P0.4
GPIO
J1_10
P0.5
GPIO
J1_11
P0.6
GPIO
J1_12
P0.7
GPIO/SW1
J1_13
P1.0
GPIO
J1_14
P1.1
GPIO
J1_15
P1.2
GPIO
J1_16
P1.3
GPIO
J1_17
P1.4
GPIO
J1_18
P1.5
GPIO
J1_19
P1.6
GPIO/LED1
J1_20
P1.7
GPIO/SAR Bypass (EXT_VREF)
J1_21
GND
Ground
J1_22
VDD
Power
Содержание verical CYPRESS CY8CKIT-049-42 Series
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Страница 68: ...CY8CKIT 049 4xxx PSoC 4 Prototyping Kit Guide Doc 001 90711 Rev J 67 Appendix ...
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