Arrow BeMicro Max 10, Руководство для начинающих пользователей

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Pinout Information for MAX 10 FPGA I/O
BeMicro Max 10 Getting Started User Guide, Version 14.0 16
3. PINOUT INFORMATION FOR MAX 10 FPGA I/O
The BeMicro Max 10 contains a variety of external peripheral devices and expansion headers connected to the MAX
10 FPGA’s configurable I/O pins. The details of the board circuitry and these connections can be found in the
schematic files included in the MAX 10 FPGA files. (Refer to Section 2.3 for details on extracting these files.) This
section presents the information in the schematic organized into pinout tables by peripheral. While the schematic
provides a board level view of all the pins for a given connector or peripherals, the tables in this section focus on the
FPGA signals needed for FPGA pin assignment and compilation.
The “Signal Name” column in the tables throughout this section indicates the naming of the signal in the Quartus
projects’ QSF
1 file provided in the various FPGA projects
3.1 Analog Devices External Peripherals
3.1.1 Accelerometer, 3-Axis, SPI interface (ADXL362)
Signal Name MAX 10 Pin
ADXL362_CS L14
ADXL362_INT1 M15
ADXL362_INT2 M14
ADXL362_MISO L18
ADXL362_MOSI L19
ADXL362_SCLK M18
3.1.2 DAC, 12-bit, SPI interface (AD5681)
Signal Name MAX 10 Pin
AD5681R_LDACn N18
AD5681R_RSTn
L15
AD5681R_SCL G17
AD5681R_SDA H17
AD5681R_SYNCn N19
1 A “QSF file” is a Quartus Settings File, a file with extension of *.qsf in which Quartus stores all project settings, including device
pin assignments.
Pinout Information for MAX 10 FPGA I/O
BeMicro Max 10 Getting Started User Guide, Version 14.0 16
3. PINOUT INFORMATION FOR MAX 10 FPGA I/O
The BeMicro Max 10 contains a variety of external peripheral devices and expansion headers connected to the MAX
10 FPGA’s configurable I/O pins. The details of the board circuitry and these connections can be found in the
schematic files included in the MAX 10 FPGA files. (Refer to Section 2.3 for details on extracting these files.) This
section presents the information in the schematic organized into pinout tables by peripheral. While the schematic
provides a board level view of all the pins for a given connector or peripherals, the tables in this section focus on the
FPGA signals needed for FPGA pin assignment and compilation.
The “Signal Name” column in the tables throughout this section indicates the naming of the signal in the Quartus
projects’ QSF
1 file provided in the various FPGA projects
3.1 Analog Devices External Peripherals
3.1.1 Accelerometer, 3-Axis, SPI interface (ADXL362)
Signal Name MAX 10 Pin
ADXL362_CS L14
ADXL362_INT1 M15
ADXL362_INT2 M14
ADXL362_MISO L18
ADXL362_MOSI L19
ADXL362_SCLK M18
3.1.2 DAC, 12-bit, SPI interface (AD5681)
Signal Name MAX 10 Pin
AD5681R_LDACn N18
AD5681R_RSTn
L15
AD5681R_SCL G17
AD5681R_SDA H17
AD5681R_SYNCn N19
1 A “QSF file” is a Quartus Settings File, a file with extension of *.qsf in which Quartus stores all project settings, including device
pin assignments.
Pinout Information for MAX 10 FPGA I/O
BeMicro Max 10 Getting Started User Guide, Version 14.0 16
3. PINOUT INFORMATION FOR MAX 10 FPGA I/O
The BeMicro Max 10 contains a variety of external peripheral devices and expansion headers connected to the MAX
10 FPGA’s configurable I/O pins. The details of the board circuitry and these connections can be found in the
schematic files included in the MAX 10 FPGA files. (Refer to Section 2.3 for details on extracting these files.) This
section presents the information in the schematic organized into pinout tables by peripheral. While the schematic
provides a board level view of all the pins for a given connector or peripherals, the tables in this section focus on the
FPGA signals needed for FPGA pin assignment and compilation.
The “Signal Name” column in the tables throughout this section indicates the naming of the signal in the Quartus
projects’ QSF
1 file provided in the various FPGA projects
3.1 Analog Devices External Peripherals
3.1.1 Accelerometer, 3-Axis, SPI interface (ADXL362)
Signal Name MAX 10 Pin
ADXL362_CS L14
ADXL362_INT1 M15
ADXL362_INT2 M14
ADXL362_MISO L18
ADXL362_MOSI L19
ADXL362_SCLK M18
3.1.2 DAC, 12-bit, SPI interface (AD5681)
Signal Name MAX 10 Pin
AD5681R_LDACn N18
AD5681R_RSTn
L15
AD5681R_SCL G17
AD5681R_SDA H17
AD5681R_SYNCn N19
1 A “QSF file” is a Quartus Settings File, a file with extension of *.qsf in which Quartus stores all project settings, including device
pin assignments.