Arnewsh SBC5307, Руководство пользователя

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3-4
Table 4 - The SBC5307 memory map
ADDRESS RANGE SIGNAL and DEVICE
$00000000-$007FFFFF /RAS1, /RAS2, 8M bytes of SDRAM’s.
$00800000-$00800FFF Internal SRAM (4K bytes)
$10000000-$100003FF Internal Module registers
$FE400000-$FE47FFFF1
External SRAM (512K bytes)
$FE600000-$FE7FFFFF /CS3, 2M Ethernet Bus area
$FFE00000-$FFEFFFFF /CS0, 1M bytes of Flash ROM.
1. Not installed. Level 2 cache footprint accepts Motorola’s MCM69F737TQ chip and any other
SRAM with the same electrical specifications and package.
All the unused area of the memory map is available to the user.
3.1.9. Reset Vector Mapping
After reset, the processor attempts to get the initial stack pointer and initial program counter values from
locations $000000-$000007 (the first eight bytes of memory space). This requires the board to have a
nonvolatile memory device in this range with proper information. However, in some systems, it is preferred
to have RAM starting at address $00000000. In MCF5307, the /CS0 responds to any accesses after reset
until the CSMR0 is written. Since /CS0 is connected to Flash ROM’s, the Flash ROMs appear to be at
address $00000000 which provides the initial stack pointer and program counter (the first 8 bytes of the
Flash ROM). The initialization routine, however, programs the chip-select logic and locates the Flash
ROM’s to start at $FFE00000 and the DRAMs to start at $00000000.
3.1.10. /TA Generation
The processor starts a bus cycle by providing the necessary information (address, R/*W, etc.) and asserting
the /TS. The processor then waits for an acknowledgment (/TA) by the addressed device before it can
complete the bus cycle. This /TA is used not only to indicate the presence of a device, it also allows
devices with different access time to communicate with the processor properly. The MCF5307, as part of
the chip-select logic, has a built in mechanism to generate the /TA for all external devices which do not
have the capability to generate the /TA on their own. The Flash ROM’s and DRAM’s can not generate the
/TA. Their chip-select logic’s are programmed by ROM Monitor to generate the /TA internally after a
preprogrammed number of wait states. In order to support the future expansion of the board, the /TA input
of the processor is also connected to the Processor Expansion Bus, J9. This allows the expansion boards to
assert this line to indicate their /TA to the processor. On the expansion boards, however, this signal should
be generated through an open collector buffer with no pull -up resistor, a pull-up resistor is included on the
board. All the /TA’s from the expansion boards should be connected to this line.
3.1.11. Wait State Generator
The Flash ROM’s and SDRAM DIMM on the board may require some adjustments on the cycle time of
the processor to make them compatible with processor speed. To extend the CPU bus cycles for the slower
devices, the chip-select logic of the MCF5307 can be programmed to generate the /TA after a given
number of wait states. Refer to Sections 3.2 and 3.3 information about wait state requirements of
SDRAM’s and Flash ROM’s respectively.