ARM Prospector P1100, Руководство пользователя, Страница: 91 / 154

Programmer’s Reference
ARM DUI 0122A Copyright © ARM Limited 2000. All rights reserved. 4-5
4.2.3 Peripheral module registers
The peripheral module registers are summarized in Table 4-3. The notes column
indicates required values and the default values set by the ARM Firmware Suite, where
appropriate. Detailed descriptions of these registers can be found in the Intel
StrongARM SA-1100 Microprocessor Developer’s Guide.
Table 4-3 Peripheral module registers
Address Register Notes
COM1 (UART0 – serial port 0)
0x8001 0000
UART1 Control Register 0 Bit 0 Parity Enable
Bit 1 Parity Select
Bit 2 Stop Bit Select
Bit 3 Data Size Select
Bit 4 Sample Clock Enable
Bit 5 Receive Clock Edge Select
Bit 6 Transmit Clock edge Select
0x8001 0004
UART1 Control Register 1 Bit 0-3 Baud Rate Divisor
0x8001 0008
UART1 Control Register 2 Bit 0-7 Baud Rate Divisor
0x8001 000C
UART1 Control Register 3 Bit 0 Receiver Enable
Bit 1 Transmitter Enable
Bit 2 Break
Bit 3 Receive FIFO Interrupt Enable
Bit 4 Transmit FIFO Interrupt Enable
Bit 5 Loopback Mode
0x8001 0010
UART1 Control Register 4
0x8001 0014
UART1 Data Register
0x8001 001C
UART1 Status Register 0 Bit 0 Transmit FIFO Service Request
Bit 1 Receive FIFO Service Request
Bit 2 Receiver Idle
Bit 3 Receiver Begin of Break
Bit 4 Receiver End of Break
Bit 5 Error in FIFO
0x8001 0020
UART1 Status Register 1 Bit 0 Transmitter Busy Flag
Bit 1 Receive FIFO Not Empty
Bit 2 Transmit FIFO Not Full
Bit 3 Parity Error
Bit 4 Framing Error
Bit 5 Receive FIFO Overrun