Hardware Description
ARM DUI 0447J
Copyright © 2009-2014, ARM. All rights reserved.
2-17
ID052914
Non-Confidential
Figure 2-7 PCIe bus architecture on the motherboard
Motherboard Express μATX
LogicTile Express
daughterboard
CoreTile Express
daughterboard
x4
x8
x8
Motherboard
Configuration
Controller
(MCC)
x4
x4
x4
PCIe1
PCIe2
HDRY
Test chip with
End Point or
Root Complex
FPGA with
End Point or
Root Complex
HDRY1
HDRY2
HDRY
PCI-Express
Switch
32 lanes
6 ports
PCI-Express slot x16, 4 lanes
Slot x 8, 4 lanes
Slot x 4, 4 lanes
Slot x4, 4 lanes
IO FPGA
SMB2
SMB1
I2C
Resets
Serial bus
interface
Reset and
configuration logic
Site 1
Site 2