H A R D W A R E D E S C R I P T I O N
DNPCIe_10G_K7_LL (_QSFP) User Manual
www.dinigroup.com
29
Figure 4 –FPGA Serial Port
There are two signals attached to the FPGA for RS232 communication:
Transmit Data – USB_B_TXD
Receive Data – USB_B_RXD
The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interface
to the USB cable.
2.2.2
Connections between FPGA and the RS232 Port
The connections between the FPGA and the RS232 Port are shown in
Table 3
.
Table 3 - Connections between RS232 Port and the FPGA
Signal Name
FPGA
RS232
USB_B_TXD
U6-G11
U15-38
USB_B_RXD
U6-F10
U15-39
2.3
QDR II+ SRAM Memory
The CY7C25632KV18-500BZC is a 1.8 V synchronous pipelined SRAM, equipped
with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture
consists of two separate ports: the read port and the write port to access the memory
array. The read port has dedicated data outputs to support read operations and the write
port has dedicated data inputs to support write operations. QDR II+ architecture has
separate data inputs and data outputs to completely eliminate the need to “turn-around”
the data bus that exists with common I/O devices. Each port is accessed through a
common address bus. Addresses for read and write addresses are latched on alternate
rising edges of the input (K) clock. Accesses to the QDR II+ read and write ports are
completely independent of one another. To maximize data throughput, both read and
write ports are equipped with DDR interfaces. Each address location is associated with
four 18-bit words that burst sequentially into or out of the device. Because data is
