H A R D W A R E D E S C R I P T I O N
DNPCIe_10G_K7_LL (_QSFP) User Manual
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2.5
EEPROM
The AT24C256C (U26) provides 262,144-bits of serial electrically erasable and
programmable read-only memory (EEPROM) organized as 32,768 words of eight bits
each. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential.
2.5.1
EEPROM Circuit Diagram
Figure 6
shows the implementation of the EEPROM memory circuit.
Figure 6 –FPGA Serial Port
Device address (A2, A1, and A0) is set up by connecting to ground and is mapped to
0000000x, where “x” is the R/W bit The eighth bit of the device address is the
read/write operation select bit. A read operation is initiated if this bit is HIGH, and a
write operation is initiated if this bit is LOW.
2.5.2
Connections between FPGA and the EEPROM
The connections between the FPGA and the EEPROM are shown in
Table 9
.
Table 9 - Connections between FPGA and the EEPROM
Signal Name
FPGA
EEPROM
EEPROM_SCL
U6-D18
U26-6
EEPROM_SDA
U6-H17
U26-5
2.6
PCI Express Interface (x4)
The Kintex-7 FPGA Integrated Block for PCI Express contains full support for
2.5Gb/s and 5.0Gb/s PCI Express Endpoint and Root Port configurations. The
LogiCORE IP Kintex-7 FPGA Integrated Block for PCI Express core internally
instantiates the Kintex-7 FPGA Integrated Block for PCI Express (PCIE_2_0). The
